mirror of https://github.com/VLSIDA/OpenRAM.git
Add check bits. Clean up logic. Move read/write bit check to next cycle.
This commit is contained in:
Matt Guthaus
parent
fe0db68965
commit
fb60b51c72
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@ -82,7 +82,6 @@ class delay(simulation):
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def create_read_port_measurement_objects(self):
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"""Create the measurements used for read ports: delays, slews, powers"""
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import pdb; pdb.set_trace()
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self.read_lib_meas = []
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self.clk_frmt = "clk{0}" # Unformatted clock name
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targ_name = "{0}{1}_{2}".format(self.dout_name,"{}",self.probe_data) # Empty values are the port and probe data bit
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@ -161,18 +160,18 @@ class delay(simulation):
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def create_debug_measurement_objects(self):
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"""Create debug measurement to help identify failures."""
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self.debug_volt_meas = []
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self.dout_volt_meas = []
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for meas in self.delay_meas:
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# Output voltage measures
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self.debug_volt_meas.append(voltage_at_measure("v_{}".format(meas.name),
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self.dout_volt_meas.append(voltage_at_measure("v_{}".format(meas.name),
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meas.targ_name_no_port))
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self.debug_volt_meas[-1].meta_str = meas.meta_str
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self.dout_volt_meas[-1].meta_str = meas.meta_str
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self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name, "FALL", "RISE", measure_scale=1e9)
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self.sen_meas.meta_str = sram_op.READ_ZERO
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self.sen_meas.meta_add_delay = True
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return self.debug_volt_meas+[self.sen_meas]
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return self.dout_volt_meas+[self.sen_meas]
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def create_read_bit_measures(self):
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""" Adds bit measurements for read0 and read1 cycles """
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@ -213,7 +212,7 @@ class delay(simulation):
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(cell_name, cell_inst) = self.sram.get_cell_name(self.sram.name, bit_row, bit_col)
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storage_names = cell_inst.mod.get_storage_net_names()
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debug.check(len(storage_names) == 2, ("Only inverting/non-inverting storage nodes"
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"supported for characterization. Storage nets={}").format(storage_names))
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"supported for characterization. Storage nets={}").format(storage_names))
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q_name = cell_name+'.'+str(storage_names[0])
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qbar_name = cell_name+'.'+str(storage_names[1])
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@ -559,8 +558,10 @@ class delay(simulation):
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meas_cycle = self.cycle_times[self.measure_cycles[port][volt_meas.meta_str]]
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# Measurement occurs at the end of the period -> current period start + period
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at_time = meas_cycle+self.period
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# Measurement occurs slightly into the next period so we know that the value
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# "stuck" after the end of the period -> current period start + 1.25*period
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at_time = meas_cycle+1.25*self.period
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return (at_time, port)
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def get_volt_when_measure_variants(self, port, volt_meas):
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@ -732,6 +733,11 @@ class delay(simulation):
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# Loop through all targeted ports and collect delays and powers.
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result = [{} for i in self.all_ports]
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# First, check that the memory has the right values at the right times
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if not self.check_bit_measures():
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return(False,{})
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for port in self.targ_write_ports:
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debug.info(2, "Checking write values for port {}".format(port))
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write_port_dict = {}
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@ -753,7 +759,6 @@ class delay(simulation):
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if not self.check_sen_measure(port):
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return (False,{})
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success = self.check_read_debug_measures(port)
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success = success and self.check_bit_measures()
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# Check timing for read ports. Power is only checked if it was read correctly
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if not self.check_valid_delays(read_port_dict) or not success:
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@ -782,7 +787,6 @@ class delay(simulation):
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# Currently, only check if the opposite than intended value was read during
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# the read cycles i.e. neither of these measurements should pass.
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success = True
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# FIXME: these checks need to be re-done to be more robust against possible errors
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bl_vals = {}
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br_vals = {}
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@ -795,28 +799,34 @@ class delay(simulation):
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debug.info(2,"{}={}".format(meas.name,val))
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bl_check = False
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for meas in self.debug_volt_meas:
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for meas in self.dout_volt_meas:
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val = meas.retrieve_measure(port=port)
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debug.info(2,"{}={}".format(meas.name, val))
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if type(val) != float:
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continue
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debug.check(type(val)==float, "Error retrieving numeric measurement: {0} {1}".format(meas.name,val))
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if meas.meta_str == sram_op.READ_ONE and val < self.vdd_voltage*0.1:
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success = False
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dout_success = False
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debug.info(1, "Debug measurement failed. Value {}V was read on read 1 cycle.".format(val))
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bl_check = self.check_bitline_meas(bl_vals[sram_op.READ_ONE], br_vals[sram_op.READ_ONE])
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bl_success = self.check_bitline_meas(bl_vals[sram_op.READ_ONE], br_vals[sram_op.READ_ONE])
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elif meas.meta_str == sram_op.READ_ZERO and val > self.vdd_voltage*0.9:
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success = False
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dout_success = False
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debug.info(1, "Debug measurement failed. Value {}V was read on read 0 cycle.".format(val))
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bl_check = self.check_bitline_meas(br_vals[sram_op.READ_ONE], bl_vals[sram_op.READ_ONE])
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bl_success = self.check_bitline_meas(br_vals[sram_op.READ_ONE], bl_vals[sram_op.READ_ONE])
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elif meas.meta_str == sram_op.READ_ONE and val > self.vdd_voltage*0.9:
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dout_success = True
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bl_success = True
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elif meas.meta_str == sram_op.READ_ZERO and val < self.vdd_voltage*0.1:
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dout_success = True
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bl_success = True
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else:
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dout_success = False
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bl_success = False
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# If the bitlines have a correct value while the output does not then that is a
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# sen error. FIXME: there are other checks that can be done to solidfy this conclusion.
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if bl_check:
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if not dout_success and bl_success:
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debug.error("Sense amp enable timing error. Increase the delay chain through the configuration file.",1)
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return success
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return dout_success
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def check_bit_measures(self):
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@ -824,7 +834,6 @@ class delay(simulation):
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Checks the measurements which represent the internal storage voltages
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at the end of the read cycle.
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"""
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success = True
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for polarity, meas_list in self.bit_meas.items():
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for meas in meas_list:
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val = meas.retrieve_measure()
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@ -839,10 +848,18 @@ class delay(simulation):
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elif (meas_cycle == sram_op.READ_ZERO and polarity == bit_polarity.INVERTING) or\
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(meas_cycle == sram_op.READ_ONE and polarity == bit_polarity.NONINVERTING):
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success = val > self.vdd_voltage/2
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elif (meas_cycle == sram_op.WRITE_ZERO and polarity == bit_polarity.INVERTING) or\
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(meas_cycle == sram_op.WRITE_ONE and polarity == bit_polarity.NONINVERTING):
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success = val > self.vdd_voltage/2
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elif (meas_cycle == sram_op.WRITE_ONE and polarity == bit_polarity.INVERTING) or\
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(meas_cycle == sram_op.WRITE_ZERO and polarity == bit_polarity.NONINVERTING):
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success = val < self.vdd_voltage/2
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else:
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success = False
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if not success:
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debug.info(1,("Wrong value detected on probe bit during read cycle. "
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"Check writes and control logic for bugs.\n measure={}, op={}, "
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"bit_storage={}, V(bit)={}").format(meas.name, meas_cycle.name, polarity.name,val))
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debug.info(1,("Wrong value detected on probe bit during read/write cycle. "
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"Check writes and control logic for bugs.\n measure={}, op={}, "
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"bit_storage={}, V(bit)={}").format(meas.name, meas_cycle.name, polarity.name,val))
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return success
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def check_bitline_meas(self, v_discharged_bl, v_charged_bl):
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@ -404,7 +404,7 @@ class bank(design.design):
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def create_bitcell_array(self):
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""" Creating Bitcell Array """
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self.bitcell_array_inst=self.add_inst(name="bitcell_array",
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self.bitcell_array_inst=self.add_inst(name="replica_bitcell_array",
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mod=self.bitcell_array)
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temp = []
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@ -53,13 +53,13 @@ class replica_column(design.design):
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self.DRC_LVS()
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def add_pins(self):
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column_list = self.cell.get_all_bitline_names()
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for cell_column in column_list:
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self.add_pin("{0}_{1}".format(cell_column,0))
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row_list = self.cell.get_all_wl_names()
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for bl_name in self.cell.get_all_bitline_names():
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self.add_pin("{0}_{1}".format(bl_name,0))
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for row in range(self.total_size):
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for cell_row in row_list:
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self.add_pin("{0}_{1}".format(cell_row,row))
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for wl_name in self.cell.get_all_wl_names():
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self.add_pin("{0}_{1}".format(wl_name,row))
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self.add_pin("vdd")
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self.add_pin("gnd")
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@ -112,21 +112,18 @@ class replica_column(design.design):
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def add_layout_pins(self):
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""" Add the layout pins """
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row_list = self.cell.get_all_wl_names()
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column_list = self.cell.get_all_bitline_names()
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for cell_column in column_list:
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bl_pin = self.cell_inst[0].get_pin(cell_column)
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self.add_layout_pin(text=cell_column,
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for bl_name in self.cell.get_all_bitline_names():
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bl_pin = self.cell_inst[0].get_pin(bl_name)
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self.add_layout_pin(text=bl_name,
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layer="metal2",
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offset=bl_pin.ll(),
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width=bl_pin.width(),
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height=self.height)
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for row in range(self.total_size):
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for cell_row in row_list:
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wl_pin = self.cell_inst[row].get_pin(cell_row)
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self.add_layout_pin(text=cell_row+"_{0}".format(row),
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for wl_name in self.cell.get_all_wl_names():
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wl_pin = self.cell_inst[row].get_pin(wl_name)
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self.add_layout_pin(text="{0}_{1}".format(wl_name,row),
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layer="metal1",
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offset=wl_pin.ll().scale(0,1),
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width=self.width,
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@ -70,6 +70,7 @@ class sram_factory:
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# Use the default name if there are default arguments
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# This is especially for library cells so that the spice and gds files can be found.
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print(module_type,len(kwargs))
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if len(kwargs)>0:
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# Create a unique name and increment the index
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module_name = "{0}_{1}".format(module_type, self.module_indices[module_type])
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