mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-29 17:39:02 +02:00
Merge branch 'master' of https://github.com/mguthaus/OpenRAM into multiport
This commit is contained in:
Michael Timothy Grimes
@@ -38,8 +38,7 @@ class lib_test(unittest.TestCase):
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# let's diff the result with a golden model
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golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),filename)
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# Randomly decided 1% difference between spice simulators is ok.
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self.assertEqual(isapproxdiff(libname,golden,0.01),True)
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self.assertEqual(isapproxdiff(libname,golden,0.15),True)
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globals.end_openram()
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@@ -36,14 +36,13 @@ class lib_test(unittest.TestCase):
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tempspice = OPTS.openram_temp + "temp.sp"
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s.sp_write(tempspice)
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filename = s.name + ".lib"
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filename = s.name + "_pruned.lib"
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libname = OPTS.openram_temp + filename
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lib.lib(libname=libname,sram=s,spfile=tempspice,use_model=False)
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# let's diff the result with a golden model
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golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),filename)
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# 15% worked in freepdk, but scmos needed 20%
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self.assertEqual(isapproxdiff(libname,golden,0.20),True)
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self.assertEqual(isapproxdiff(libname,golden,0.30),True)
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OPTS.analytical_delay = True
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reload(characterizer)
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@@ -42,7 +42,7 @@ class lib_test(unittest.TestCase):
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|
||||
# let's diff the result with a golden model
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golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),filename)
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self.assertEqual(isapproxdiff(libname,golden,0.25),True)
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self.assertEqual(isapproxdiff(libname,golden,0.15),True)
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OPTS.analytical_delay = True
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OPTS.trim_netlist = True
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@@ -21,7 +21,6 @@ class lef_test(unittest.TestCase):
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OPTS.check_lvsdrc = False
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import sram
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import lef
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debug.info(1, "Testing LEF for sample 2 bit, 16 words SRAM with 1 bank")
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s = sram.sram(word_size=2,
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@@ -36,7 +35,7 @@ class lef_test(unittest.TestCase):
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gdsname = OPTS.openram_temp + gdsfile
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lefname = OPTS.openram_temp + leffile
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s.gds_write(gdsname)
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lef.lef(gdsname,lefname,s)
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s.lef_write(lefname)
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# let's diff the result with a golden model
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golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),leffile)
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@@ -21,7 +21,6 @@ class verilog_test(unittest.TestCase):
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OPTS.check_lvsdrc = False
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import sram
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import verilog
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debug.info(1, "Testing Verilog for sample 2 bit, 16 words SRAM with 1 bank")
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s = sram.sram(word_size=2,
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@@ -33,7 +32,7 @@ class verilog_test(unittest.TestCase):
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vfile = s.name + ".v"
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vname = OPTS.openram_temp + vfile
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verilog.verilog(vname,s)
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s.verilog_write(vname)
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# let's diff the result with a golden model
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+5354
-13991
File diff suppressed because it is too large
Load Diff
@@ -74,7 +74,7 @@ cell (sram_2_16_1_freepdk45){
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dont_use : true;
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map_only : true;
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dont_touch : true;
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area : 696.39825;
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area : 0.023625;
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bus(DATA){
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bus_type : DATA;
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@@ -92,10 +92,10 @@ cell (sram_2_16_1_freepdk45){
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internal_power(){
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when : "OEb & !clk";
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rise_power(scalar){
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values("0.0308667");
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values("0.027781");
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}
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fall_power(scalar){
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values("0.0304125");
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values("0.026752");
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}
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}
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timing(){
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@@ -129,10 +129,10 @@ cell (sram_2_16_1_freepdk45){
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internal_power(){
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when : "!OEb & !clk";
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rise_power(scalar){
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values("0.0362061");
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values("0.031198");
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}
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fall_power(scalar){
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values("0.0364614");
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values("0.031252");
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}
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||||
}
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timing(){
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@@ -140,23 +140,23 @@ cell (sram_2_16_1_freepdk45){
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related_pin : "clk";
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timing_type : falling_edge;
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cell_rise(CELL_TABLE) {
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values("0.047, 0.048, 0.055",\
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"0.048, 0.049, 0.056",\
|
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"0.053, 0.054, 0.061");
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values("0.046, 0.047, 0.054",\
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"0.047, 0.047, 0.054",\
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"0.052, 0.052, 0.059");
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}
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cell_fall(CELL_TABLE) {
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values("0.143, 0.144, 0.152",\
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"0.144, 0.145, 0.153",\
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"0.149, 0.15, 0.158");
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values("0.132, 0.133, 0.142",\
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"0.133, 0.134, 0.142",\
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"0.138, 0.139, 0.147");
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}
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rise_transition(CELL_TABLE) {
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values("0.014, 0.015, 0.027",\
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"0.014, 0.015, 0.027",\
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||||
"0.014, 0.016, 0.027");
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"0.014, 0.015, 0.027");
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}
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fall_transition(CELL_TABLE) {
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values("0.019, 0.02, 0.035",\
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"0.019, 0.02, 0.035",\
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values("0.018, 0.02, 0.036",\
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"0.019, 0.02, 0.036",\
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"0.019, 0.02, 0.036");
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}
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}
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@@ -308,20 +308,20 @@ cell (sram_2_16_1_freepdk45){
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timing_type :"min_pulse_width";
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related_pin : clk;
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rise_constraint(scalar) {
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values("0.205");
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values("0.1955");
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||||
}
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fall_constraint(scalar) {
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values("0.205");
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||||
values("0.1955");
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||||
}
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||||
}
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||||
timing(){
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timing_type :"minimum_period";
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related_pin : clk;
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||||
rise_constraint(scalar) {
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||||
values("0.41");
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values("0.391");
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||||
}
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||||
fall_constraint(scalar) {
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||||
values("0.41");
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values("0.391");
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}
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}
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||||
}
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@@ -74,7 +74,7 @@ cell (sram_2_16_1_freepdk45){
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dont_use : true;
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map_only : true;
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dont_touch : true;
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area : 692.2795;
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||||
area : 0.023625;
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bus(DATA){
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bus_type : DATA;
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@@ -140,14 +140,14 @@ cell (sram_2_16_1_freepdk45){
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||||
related_pin : "clk";
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timing_type : falling_edge;
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cell_rise(CELL_TABLE) {
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values("0.122, 0.123, 0.132",\
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"0.122, 0.123, 0.132",\
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"0.122, 0.123, 0.132");
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values("0.123, 0.124, 0.133",\
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"0.123, 0.124, 0.133",\
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||||
"0.123, 0.124, 0.133");
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}
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cell_fall(CELL_TABLE) {
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values("0.122, 0.123, 0.132",\
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"0.122, 0.123, 0.132",\
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"0.122, 0.123, 0.132");
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||||
values("0.123, 0.124, 0.133",\
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||||
"0.123, 0.124, 0.133",\
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||||
"0.123, 0.124, 0.133");
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||||
}
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||||
rise_transition(CELL_TABLE) {
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values("0.006, 0.007, 0.018",\
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@@ -0,0 +1,329 @@
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library (sram_2_16_1_freepdk45_lib){
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delay_model : "table_lookup";
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time_unit : "1ns" ;
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voltage_unit : "1v" ;
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current_unit : "1mA" ;
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resistance_unit : "1kohm" ;
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capacitive_load_unit(1 ,fF) ;
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leakage_power_unit : "1mW" ;
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pulling_resistance_unit :"1kohm" ;
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operating_conditions(TT){
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voltage : 1.0 ;
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temperature : 25.000 ;
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}
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input_threshold_pct_fall : 50.0 ;
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output_threshold_pct_fall : 50.0 ;
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input_threshold_pct_rise : 50.0 ;
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||||
output_threshold_pct_rise : 50.0 ;
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slew_lower_threshold_pct_fall : 10.0 ;
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slew_upper_threshold_pct_fall : 90.0 ;
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slew_lower_threshold_pct_rise : 10.0 ;
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slew_upper_threshold_pct_rise : 90.0 ;
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default_cell_leakage_power : 0.0 ;
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default_leakage_power_density : 0.0 ;
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default_input_pin_cap : 1.0 ;
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default_inout_pin_cap : 1.0 ;
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default_output_pin_cap : 0.0 ;
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default_max_transition : 0.5 ;
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default_fanout_load : 1.0 ;
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default_max_fanout : 4.0 ;
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default_connection_class : universal ;
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lu_table_template(CELL_TABLE){
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variable_1 : input_net_transition;
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variable_2 : total_output_net_capacitance;
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index_1("0.00125, 0.005, 0.04");
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index_2("0.052275, 0.2091, 1.6728");
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}
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lu_table_template(CONSTRAINT_TABLE){
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variable_1 : related_pin_transition;
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variable_2 : constrained_pin_transition;
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index_1("0.00125, 0.005, 0.04");
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index_2("0.00125, 0.005, 0.04");
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}
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default_operating_conditions : TT;
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|
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|
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type (DATA){
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base_type : array;
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data_type : bit;
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bit_width : 2;
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bit_from : 0;
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bit_to : 1;
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}
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type (ADDR){
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base_type : array;
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data_type : bit;
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bit_width : 4;
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bit_from : 0;
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bit_to : 3;
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}
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cell (sram_2_16_1_freepdk45){
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memory(){
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type : ram;
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address_width : 4;
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word_width : 2;
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}
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interface_timing : true;
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dont_use : true;
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map_only : true;
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dont_touch : true;
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area : 0.023625;
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||||
bus(DATA){
|
||||
bus_type : DATA;
|
||||
direction : inout;
|
||||
max_capacitance : 1.6728;
|
||||
three_state : "!OEb & !clk";
|
||||
memory_write(){
|
||||
address : ADDR;
|
||||
clocked_on : clk;
|
||||
}
|
||||
memory_read(){
|
||||
address : ADDR;
|
||||
}
|
||||
pin(DATA[1:0]){
|
||||
internal_power(){
|
||||
when : "OEb & !clk";
|
||||
rise_power(scalar){
|
||||
values("0.027781");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.026752");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!OEb & !clk";
|
||||
rise_power(scalar){
|
||||
values("0.031198");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.031252");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk";
|
||||
timing_type : falling_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.046, 0.047, 0.054",\
|
||||
"0.047, 0.047, 0.054",\
|
||||
"0.052, 0.052, 0.059");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("0.132, 0.133, 0.142",\
|
||||
"0.133, 0.134, 0.142",\
|
||||
"0.138, 0.139, 0.147");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.014, 0.015, 0.027",\
|
||||
"0.014, 0.015, 0.027",\
|
||||
"0.014, 0.015, 0.027");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.018, 0.02, 0.036",\
|
||||
"0.019, 0.02, 0.036",\
|
||||
"0.019, 0.02, 0.036");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bus(ADDR){
|
||||
bus_type : ADDR;
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
max_transition : 0.04;
|
||||
fanout_load : 1.000000;
|
||||
pin(ADDR[3:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(CSb){
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(OEb){
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(WEb){
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(clk){
|
||||
clock : true;
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk;
|
||||
rise_constraint(scalar) {
|
||||
values("0.1955");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.1955");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk;
|
||||
rise_constraint(scalar) {
|
||||
values("0.391");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.391");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -74,7 +74,7 @@ cell (sram_2_16_1_scn3me_subm){
|
||||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 90431.64;
|
||||
area : 2.7;
|
||||
|
||||
bus(DATA){
|
||||
bus_type : DATA;
|
||||
@@ -92,10 +92,10 @@ cell (sram_2_16_1_scn3me_subm){
|
||||
internal_power(){
|
||||
when : "OEb & !clk";
|
||||
rise_power(scalar){
|
||||
values("3.1581");
|
||||
values("3.2612");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("3.4945");
|
||||
values("3.5985");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
@@ -129,10 +129,10 @@ cell (sram_2_16_1_scn3me_subm){
|
||||
internal_power(){
|
||||
when : "!OEb & !clk";
|
||||
rise_power(scalar){
|
||||
values("5.0577");
|
||||
values("5.1597");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("5.0831");
|
||||
values("5.1863");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
@@ -140,24 +140,24 @@ cell (sram_2_16_1_scn3me_subm){
|
||||
related_pin : "clk";
|
||||
timing_type : falling_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.542, 0.626, 1.298",\
|
||||
"0.544, 0.627, 1.304",\
|
||||
"0.594, 0.674, 1.35");
|
||||
values("0.509, 0.592, 1.265",\
|
||||
"0.512, 0.595, 1.271",\
|
||||
"0.561, 0.642, 1.317");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("1.535, 1.637, 2.604",\
|
||||
"1.54, 1.641, 2.612",\
|
||||
"1.59, 1.693, 2.662");
|
||||
values("1.449, 1.549, 2.511",\
|
||||
"1.453, 1.555, 2.518",\
|
||||
"1.505, 1.607, 2.568");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.191, 0.337, 1.883",\
|
||||
"0.193, 0.338, 1.885",\
|
||||
"0.195, 0.341, 1.884");
|
||||
values("0.19, 0.335, 1.887",\
|
||||
"0.192, 0.336, 1.886",\
|
||||
"0.194, 0.339, 1.886");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.252, 0.446, 2.468",\
|
||||
"0.253, 0.448, 2.448",\
|
||||
"0.253, 0.447, 2.454");
|
||||
values("0.282, 0.465, 2.464",\
|
||||
"0.283, 0.466, 2.463",\
|
||||
"0.283, 0.465, 2.455");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -74,7 +74,7 @@ cell (sram_2_16_1_scn3me_subm){
|
||||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 90431.64;
|
||||
area : 2.7;
|
||||
|
||||
bus(DATA){
|
||||
bus_type : DATA;
|
||||
|
||||
@@ -0,0 +1,329 @@
|
||||
library (sram_2_16_1_scn3me_subm_lib){
|
||||
delay_model : "table_lookup";
|
||||
time_unit : "1ns" ;
|
||||
voltage_unit : "1v" ;
|
||||
current_unit : "1mA" ;
|
||||
resistance_unit : "1kohm" ;
|
||||
capacitive_load_unit(1 ,fF) ;
|
||||
leakage_power_unit : "1mW" ;
|
||||
pulling_resistance_unit :"1kohm" ;
|
||||
operating_conditions(TT){
|
||||
voltage : 5.0 ;
|
||||
temperature : 25.000 ;
|
||||
}
|
||||
|
||||
input_threshold_pct_fall : 50.0 ;
|
||||
output_threshold_pct_fall : 50.0 ;
|
||||
input_threshold_pct_rise : 50.0 ;
|
||||
output_threshold_pct_rise : 50.0 ;
|
||||
slew_lower_threshold_pct_fall : 10.0 ;
|
||||
slew_upper_threshold_pct_fall : 90.0 ;
|
||||
slew_lower_threshold_pct_rise : 10.0 ;
|
||||
slew_upper_threshold_pct_rise : 90.0 ;
|
||||
|
||||
default_cell_leakage_power : 0.0 ;
|
||||
default_leakage_power_density : 0.0 ;
|
||||
default_input_pin_cap : 1.0 ;
|
||||
default_inout_pin_cap : 1.0 ;
|
||||
default_output_pin_cap : 0.0 ;
|
||||
default_max_transition : 0.5 ;
|
||||
default_fanout_load : 1.0 ;
|
||||
default_max_fanout : 4.0 ;
|
||||
default_connection_class : universal ;
|
||||
|
||||
lu_table_template(CELL_TABLE){
|
||||
variable_1 : input_net_transition;
|
||||
variable_2 : total_output_net_capacitance;
|
||||
index_1("0.0125, 0.05, 0.4");
|
||||
index_2("2.45605, 9.8242, 78.5936");
|
||||
}
|
||||
|
||||
lu_table_template(CONSTRAINT_TABLE){
|
||||
variable_1 : related_pin_transition;
|
||||
variable_2 : constrained_pin_transition;
|
||||
index_1("0.0125, 0.05, 0.4");
|
||||
index_2("0.0125, 0.05, 0.4");
|
||||
}
|
||||
|
||||
default_operating_conditions : TT;
|
||||
|
||||
|
||||
type (DATA){
|
||||
base_type : array;
|
||||
data_type : bit;
|
||||
bit_width : 2;
|
||||
bit_from : 0;
|
||||
bit_to : 1;
|
||||
}
|
||||
|
||||
type (ADDR){
|
||||
base_type : array;
|
||||
data_type : bit;
|
||||
bit_width : 4;
|
||||
bit_from : 0;
|
||||
bit_to : 3;
|
||||
}
|
||||
|
||||
cell (sram_2_16_1_scn3me_subm){
|
||||
memory(){
|
||||
type : ram;
|
||||
address_width : 4;
|
||||
word_width : 2;
|
||||
}
|
||||
interface_timing : true;
|
||||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 2.7;
|
||||
|
||||
bus(DATA){
|
||||
bus_type : DATA;
|
||||
direction : inout;
|
||||
max_capacitance : 78.5936;
|
||||
three_state : "!OEb & !clk";
|
||||
memory_write(){
|
||||
address : ADDR;
|
||||
clocked_on : clk;
|
||||
}
|
||||
memory_read(){
|
||||
address : ADDR;
|
||||
}
|
||||
pin(DATA[1:0]){
|
||||
internal_power(){
|
||||
when : "OEb & !clk";
|
||||
rise_power(scalar){
|
||||
values("2.8745");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("3.0265");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.082, 0.088, 0.186",\
|
||||
"0.082, 0.088, 0.186",\
|
||||
"0.082, 0.088, 0.186");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.021, 0.021, 0.027",\
|
||||
"0.021, 0.021, 0.027",\
|
||||
"0.021, 0.021, 0.027");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.015, 0.021",\
|
||||
"0.009, 0.015, 0.021",\
|
||||
"0.009, 0.015, 0.021");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.065, -0.071, -0.175",\
|
||||
"-0.065, -0.071, -0.175",\
|
||||
"-0.065, -0.071, -0.175");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!OEb & !clk";
|
||||
rise_power(scalar){
|
||||
values("4.4921");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("4.5139");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk";
|
||||
timing_type : falling_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.496, 0.579, 1.253",\
|
||||
"0.499, 0.581, 1.258",\
|
||||
"0.547, 0.627, 1.305");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("1.429, 1.539, 2.523",\
|
||||
"1.433, 1.544, 2.526",\
|
||||
"1.485, 1.595, 2.578");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.189, 0.335, 1.879",\
|
||||
"0.19, 0.336, 1.879",\
|
||||
"0.192, 0.337, 1.879");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.224, 0.437, 2.462",\
|
||||
"0.225, 0.437, 2.472",\
|
||||
"0.225, 0.436, 2.458");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bus(ADDR){
|
||||
bus_type : ADDR;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
max_transition : 0.4;
|
||||
fanout_load : 1.000000;
|
||||
pin(ADDR[3:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.082, 0.088, 0.186",\
|
||||
"0.082, 0.088, 0.186",\
|
||||
"0.082, 0.088, 0.186");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.021, 0.021, 0.027",\
|
||||
"0.021, 0.021, 0.027",\
|
||||
"0.021, 0.021, 0.027");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.015, 0.021",\
|
||||
"0.009, 0.015, 0.021",\
|
||||
"0.009, 0.015, 0.021");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.065, -0.071, -0.175",\
|
||||
"-0.065, -0.071, -0.175",\
|
||||
"-0.065, -0.071, -0.175");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(CSb){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.082, 0.088, 0.186",\
|
||||
"0.082, 0.088, 0.186",\
|
||||
"0.082, 0.088, 0.186");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.021, 0.021, 0.027",\
|
||||
"0.021, 0.021, 0.027",\
|
||||
"0.021, 0.021, 0.027");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.015, 0.021",\
|
||||
"0.009, 0.015, 0.021",\
|
||||
"0.009, 0.015, 0.021");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.065, -0.071, -0.175",\
|
||||
"-0.065, -0.071, -0.175",\
|
||||
"-0.065, -0.071, -0.175");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(OEb){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.082, 0.088, 0.186",\
|
||||
"0.082, 0.088, 0.186",\
|
||||
"0.082, 0.088, 0.186");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.021, 0.021, 0.027",\
|
||||
"0.021, 0.021, 0.027",\
|
||||
"0.021, 0.021, 0.027");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.015, 0.021",\
|
||||
"0.009, 0.015, 0.021",\
|
||||
"0.009, 0.015, 0.021");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.065, -0.071, -0.175",\
|
||||
"-0.065, -0.071, -0.175",\
|
||||
"-0.065, -0.071, -0.175");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(WEb){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.082, 0.088, 0.186",\
|
||||
"0.082, 0.088, 0.186",\
|
||||
"0.082, 0.088, 0.186");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.021, 0.021, 0.027",\
|
||||
"0.021, 0.021, 0.027",\
|
||||
"0.021, 0.021, 0.027");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.015, 0.021",\
|
||||
"0.009, 0.015, 0.021",\
|
||||
"0.009, 0.015, 0.021");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.065, -0.071, -0.175",\
|
||||
"-0.065, -0.071, -0.175",\
|
||||
"-0.065, -0.071, -0.175");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(clk){
|
||||
clock : true;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk;
|
||||
rise_constraint(scalar) {
|
||||
values("4.375");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("4.375");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk;
|
||||
rise_constraint(scalar) {
|
||||
values("8.75");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("8.75");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user