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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev

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This commit is contained in:
mrg
2020-11-04 10:40:20 -08:00
parent 8c4584daa1 6e12d4d46c
commit fb0b285652
349 changed files with 3398 additions and 3618 deletions
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compiler/tests/00_code_format_check_test.py
+3 -3
View File
@@ -9,7 +9,7 @@
import unittest
from testutils import *
import sys,os,re
import sys, os,re
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
import debug
@@ -27,7 +27,7 @@ class code_format_test(openram_test):
if re.search("gdsMill", code):
continue
errors += check_file_format_tab(code)
errors += check_file_format_carriage(code)
errors += check_file_format_carriage(code)
for code in source_codes:
if re.search("gdsMill", code):
@@ -79,7 +79,7 @@ def check_file_format_tab(file_name):
def check_file_format_carriage(file_name):
"""
Check if file contains carriage returns at the end of lines
Check if file contains carriage returns at the end of lines
and return the number of carriage return lines.
"""
compiler/tests/01_library_drc_test.py
+3 -3
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os,re
import sys, os,re
#sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -25,7 +25,7 @@ class library_drc_test(openram_test):
drc_errors = 0
debug.info(1, "\nPerforming DRC on: " + ", ".join(allnames))
for f in allnames:
gds_name = "{0}/{1}.gds".format(gds_dir, f)
gds_name = "{0}/{1}.gds".format(gds_dir, f)
if not os.path.isfile(gds_name):
drc_errors += 1
debug.error("Missing GDS file: {}".format(gds_name))
@@ -43,7 +43,7 @@ def setup_files():
gds_files = list(filter(nametest.search, files))
tempnames = gds_files
# remove the .gds and .sp suffixes
for i in range(len(tempnames)):
gds_files[i] = re.sub('\.gds$', '', tempnames[i])
compiler/tests/02_library_lvs_test.py
+1 -1
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os,re
import sys, os,re
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
compiler/tests/03_contact_test.py
+6 -6
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -32,7 +32,7 @@ class contact_test(openram_test):
debug.info(2, "1 x 1 {} test".format(stack_name))
c = factory.create(module_type="contact", layer_stack=layer_stack, dimensions=(1, 1), directions=("H", "H"))
self.local_drc_check(c)
# Check single 1 x 1 contact"
debug.info(2, "1 x 1 {} test".format(stack_name))
c = factory.create(module_type="contact", layer_stack=layer_stack, dimensions=(1, 1), directions=("H","V"))
@@ -51,7 +51,7 @@ class contact_test(openram_test):
# Only do multiple contacts for BEOL
for layer_stack in beol_stacks:
stack_name = ":".join(map(str, layer_stack))
# check vertical array with one in the middle and two ends
debug.info(2, "1 x 3 {} test".format(stack_name))
c = factory.create(module_type="contact", layer_stack=layer_stack, dimensions=(1, 3))
@@ -71,7 +71,7 @@ class contact_test(openram_test):
# check vertical array with one in the middle and two ends
layer_stack = active_stack
stack_name = ":".join(map(str, layer_stack))
debug.info(2, "1 x 1 {} nwell".format(stack_name))
c = factory.create(module_type="contact",
layer_stack=layer_stack,
@@ -85,9 +85,9 @@ class contact_test(openram_test):
implant_type="p",
well_type="p")
self.local_drc_check(c)
globals.end_openram()
# run the test from the command line
compiler/tests/03_path_test.py
+2 -2
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -87,7 +87,7 @@ class path_test(openram_test):
self.local_drc_check(w)
globals.end_openram()
# run the test from the command line
compiler/tests/03_ptx_1finger_nmos_test.py
+1 -1
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
compiler/tests/03_ptx_1finger_pmos_test.py
+1 -1
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
compiler/tests/03_ptx_3finger_nmos_test.py
+1 -1
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
compiler/tests/03_ptx_3finger_pmos_test.py
+2 -2
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -33,7 +33,7 @@ class ptx_3finger_pmos_test(openram_test):
self.local_drc_check(fet)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
compiler/tests/03_ptx_4finger_nmos_test.py
+1 -1
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
compiler/tests/03_ptx_4finger_pmos_test.py
+2 -2
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -33,7 +33,7 @@ class ptx_test(openram_test):
self.local_drc_check(fet)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
compiler/tests/03_ptx_no_contacts_test.py
+2 -2
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -48,7 +48,7 @@ class ptx_no_contacts_test(openram_test):
series_devices=True,
tx_type="nmos")
self.local_drc_check(fet)
globals.end_openram()
compiler/tests/03_wire_test.py
+1 -1
View File
@@ -51,7 +51,7 @@ class wire_test(openram_test):
self.local_drc_check(w)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
compiler/tests/04_and2_dec_test.py
+3 -2
View File
@@ -8,13 +8,14 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class and2_dec_test(openram_test):
def runTest(self):
@@ -27,7 +28,7 @@ class and2_dec_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Testing and2_dec gate")
a = factory.create(module_type="and2_dec")
self.local_check(a)
compiler/tests/04_and3_dec_test.py
+2 -2
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -27,7 +27,7 @@ class and3_dec_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Testing and3_dec gate")
a = factory.create(module_type="and3_dec")
self.local_check(a)
compiler/tests/04_and4_dec_test.py
+1 -1
View File
@@ -29,7 +29,7 @@ class and4_dec_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Testing and4_dec gate")
a = factory.create(module_type="and4_dec")
self.local_check(a)
compiler/tests/04_column_mux_1rw_1r_test.py
+2 -2
View File
@@ -26,7 +26,7 @@ class column_mux_1rw_1r_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Checking column mux port 0")
tx = factory.create(module_type="column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(tx)
@@ -34,7 +34,7 @@ class column_mux_1rw_1r_test(openram_test):
debug.info(2, "Checking column mux port 1")
tx = factory.create(module_type="column_mux", tx_size=8, bitcell_bl="bl1", bitcell_br="br1")
self.local_check(tx)
globals.end_openram()
# run the test from the command line
compiler/tests/04_dff_buf_test.py
+2 -2
View File
@@ -8,19 +8,19 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class dff_buf_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(2, "Testing dff_buf 4x 8x")
a = factory.create(module_type="dff_buf", inv1_size=4, inv2_size=8)
self.local_check(a)
compiler/tests/04_dummy_pbitcell_test.py
+4 -4
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -21,7 +21,7 @@ class replica_pbitcell_test(openram_test):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import dummy_pbitcell
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
@@ -31,7 +31,7 @@ class replica_pbitcell_test(openram_test):
debug.info(2, "Checking dummy bitcell using pbitcell (small cell)")
tx = dummy_pbitcell.dummy_pbitcell(name="rpbc")
self.local_check(tx)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 1
@@ -42,7 +42,7 @@ class replica_pbitcell_test(openram_test):
self.local_check(tx)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/04_pbitcell_test.py
+8 -8
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -37,7 +37,7 @@ class pbitcell_test(openram_test):
debug.info(2, "Bitcell with 0 read/write ports")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=1
OPTS.num_w_ports=0
OPTS.num_r_ports=1
@@ -45,7 +45,7 @@ class pbitcell_test(openram_test):
debug.info(2, "Bitcell with 0 write ports")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=1
OPTS.num_w_ports=1
OPTS.num_r_ports=0
@@ -53,7 +53,7 @@ class pbitcell_test(openram_test):
debug.info(2, "Bitcell with 0 read ports")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=1
OPTS.num_w_ports=0
OPTS.num_r_ports=0
@@ -69,7 +69,7 @@ class pbitcell_test(openram_test):
debug.info(2, "Bitcell with 2 of each port: read/write, write, and read")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=0
OPTS.num_w_ports=2
OPTS.num_r_ports=2
@@ -77,7 +77,7 @@ class pbitcell_test(openram_test):
debug.info(2, "Bitcell with 0 read/write ports")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=2
OPTS.num_w_ports=0
OPTS.num_r_ports=2
@@ -85,7 +85,7 @@ class pbitcell_test(openram_test):
debug.info(2, "Bitcell with 0 write ports")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=2
OPTS.num_w_ports=2
OPTS.num_r_ports=0
@@ -93,7 +93,7 @@ class pbitcell_test(openram_test):
debug.info(2, "Bitcell with 0 read ports")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=2
OPTS.num_w_ports=0
OPTS.num_r_ports=0
compiler/tests/04_pbuf_dec_8x_test.py
+2 -2
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -25,7 +25,7 @@ class pbuf_dec_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Checking 8x size decoder buffer")
a = factory.create(module_type="pbuf_dec", size=8)
self.local_check(a)
compiler/tests/04_pbuf_test.py
+1 -1
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
compiler/tests/04_pdriver_test.py
+6 -6
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -25,19 +25,19 @@ class pdriver_test(openram_test):
# a tests the error message for specifying conflicting conditions
#a = pdriver.pdriver(fanout = 4,size_list = [1,2,4,8])
#self.local_check(a)
b = factory.create(module_type="pdriver", size_list = [1,2,4,8])
self.local_check(b)
c = factory.create(module_type="pdriver", fanout = 50)
self.local_check(c)
d = factory.create(module_type="pdriver", fanout = 50, inverting = True)
self.local_check(d)
e = factory.create(module_type="pdriver", fanout = 64)
self.local_check(e)
f = factory.create(module_type="pdriver", fanout = 64, inverting = True)
self.local_check(f)
compiler/tests/04_pinv_100x_test.py
+1 -1
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
compiler/tests/04_pinv_10x_test.py
+2 -2
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -25,7 +25,7 @@ class pinv_test(openram_test):
tx = factory.create(module_type="pinv", size=8)
self.local_check(tx)
globals.end_openram()
globals.end_openram()
# run the test from the command line
compiler/tests/04_pinv_1x_beta_test.py
+2 -2
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -25,7 +25,7 @@ class pinv_test(openram_test):
tx = factory.create(module_type="pinv", size=1, beta=3)
self.local_check(tx)
globals.end_openram()
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
compiler/tests/04_pinv_1x_test.py
+1 -1
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
compiler/tests/04_pinv_2x_test.py
+2 -2
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -25,7 +25,7 @@ class pinv_test(openram_test):
tx = factory.create(module_type="pinv", size=2)
self.local_check(tx)
globals.end_openram()
globals.end_openram()
# run the test from the command line
compiler/tests/04_pinv_dec_1x_test.py
+3 -2
View File
@@ -8,13 +8,14 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class pinv_dec_1x_test(openram_test):
def runTest(self):
@@ -25,7 +26,7 @@ class pinv_dec_1x_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Checking 1x size decoder inverter")
tx = factory.create(module_type="pinv_dec", size=1)
self.local_check(tx)
compiler/tests/04_pinvbuf_test.py
+1 -1
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
compiler/tests/04_pnand2_test.py
+3 -3
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -29,9 +29,9 @@ class pnand2_test(openram_test):
# tx = factory.create(module_type="pnand2", size=1, add_wells=False)
# # Only DRC because well contacts will fail LVS
# self.local_drc_check(tx)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
compiler/tests/04_pnand3_test.py
+2 -2
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -31,7 +31,7 @@ class pnand3_test(openram_test):
# self.local_drc_check(tx)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
compiler/tests/04_pnand4_test.py
+1 -1
View File
@@ -27,7 +27,7 @@ class pnand4_test(openram_test):
self.local_check(tx)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
compiler/tests/04_pnor2_test.py
+2 -2
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -26,7 +26,7 @@ class pnor2_test(openram_test):
self.local_check(tx)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/04_precharge_1rw_1r_test.py
+3 -3
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -21,7 +21,7 @@ class precharge_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# check precharge array in multi-port
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
@@ -38,7 +38,7 @@ class precharge_test(openram_test):
self.local_check(tx)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/04_precharge_pbitcell_test.py
+1 -1
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
compiler/tests/04_precharge_test.py
+4 -4
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -21,14 +21,14 @@ class precharge_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# check precharge in single port
debug.info(2, "Checking precharge for handmade bitcell")
tx = factory.create(module_type="precharge", size=1)
self.local_check(tx)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/04_pwrite_driver_test.py
+1 -1
View File
@@ -26,7 +26,7 @@ class pwrite_driver_test(openram_test):
tx = factory.create(module_type="pwrite_driver", size=1)
self.local_check(tx)
globals.end_openram()
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
compiler/tests/04_replica_pbitcell_test.py
+4 -4
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -21,7 +21,7 @@ class replica_pbitcell_test(openram_test):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import replica_pbitcell
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
@@ -31,7 +31,7 @@ class replica_pbitcell_test(openram_test):
debug.info(2, "Checking replica bitcell using pbitcell (small cell)")
tx = replica_pbitcell.replica_pbitcell(name="rpbc")
self.local_check(tx)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 1
@@ -42,7 +42,7 @@ class replica_pbitcell_test(openram_test):
self.local_check(tx)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/04_wordline_driver_test.py
+1 -1
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
compiler/tests/05_bitcell_array_1rw_1r_test.py
+4 -5
View File
@@ -8,30 +8,29 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 05_bitcell_1rw_1r_array_test")
class bitcell_array_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Testing 4x4 array for cell_1rw_1r")
a = factory.create(module_type="bitcell_array", cols=4, rows=4)
self.local_check(a)
globals.end_openram()
# run the test from the command line
compiler/tests/05_bitcell_array_test.py
+2 -2
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -26,7 +26,7 @@ class array_test(openram_test):
debug.info(2, "Testing 8x8 array for 6t_cell")
a = factory.create(module_type="bitcell_array", cols=8, rows=8)
self.local_check(a)
globals.end_openram()
# run the test from the command line
compiler/tests/05_dummy_array_test.py
+3 -3
View File
@@ -1,12 +1,12 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2019 Regents of the University of California
# Copyright (c) 2016-2019 Regents of the University of California
# All rights reserved.
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -26,7 +26,7 @@ class dummy_row_test(openram_test):
debug.info(2, "Testing dummy column for 6t_cell")
a = factory.create(module_type="dummy_array", rows=4, cols=1)
self.local_check(a)
globals.end_openram()
# run the test from the command line
compiler/tests/05_pbitcell_array_test.py
+3 -3
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -29,7 +29,7 @@ class pbitcell_array_test(openram_test):
OPTS.num_w_ports = 2
a = factory.create(module_type="bitcell_array", cols=4, rows=4)
self.local_check(a)
debug.info(2, "Testing 4x4 array for multiport bitcell, with write ports at the edge of the bit cell")
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 2
@@ -37,7 +37,7 @@ class pbitcell_array_test(openram_test):
OPTS.num_w_ports = 2
a = factory.create(module_type="bitcell_array", cols=4, rows=4)
self.local_check(a)
debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell")
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 2
compiler/tests/06_hierarchical_decoder_1rw_1r_test.py
+4 -4
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -27,7 +27,7 @@ class hierarchical_decoder_1rw_1r_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
# Checks 2x4 and 2-input NAND decoder
debug.info(1, "Testing 16 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=16)
@@ -57,9 +57,9 @@ class hierarchical_decoder_1rw_1r_test(openram_test):
debug.info(1, "Testing 512 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=512)
self.local_check(a)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/06_hierarchical_decoder_pbitcell_test.py
+3 -2
View File
@@ -8,13 +8,14 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class hierarchical_decoder_pbitcell_test(openram_test):
def runTest(self):
@@ -25,7 +26,7 @@ class hierarchical_decoder_pbitcell_test(openram_test):
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
globals.setup_bitcell()
factory.reset()
debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)")
a = factory.create(module_type="hierarchical_decoder", num_outputs=16)
compiler/tests/06_hierarchical_decoder_test.py
+3 -4
View File
@@ -22,11 +22,10 @@ class hierarchical_decoder_test(openram_test):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# Use the 2 port cell since it is usually bigger/easier
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
# Checks 2x4 and 2-input NAND decoder
debug.info(1, "Testing 16 row sample for hierarchical_decoder")
@@ -62,9 +61,9 @@ class hierarchical_decoder_test(openram_test):
debug.info(1, "Testing 4096 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=4096)
self.local_check(a)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py
+2 -2
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -26,7 +26,7 @@ class hierarchical_predecode2x4_1rw_1r_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(1, "Testing sample for hierarchy_predecode2x4")
a = factory.create(module_type="hierarchical_predecode2x4")
self.local_check(a)
compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py
+3 -2
View File
@@ -8,13 +8,14 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class hierarchical_predecode2x4_pbitcell_test(openram_test):
def runTest(self):
@@ -26,7 +27,7 @@ class hierarchical_predecode2x4_pbitcell_test(openram_test):
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
globals.setup_bitcell()
debug.info(1, "Testing sample for hierarchy_predecode2x4 (multi-port case)")
a = factory.create(module_type="hierarchical_predecode2x4")
self.local_check(a)
compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py
+2 -2
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -27,7 +27,7 @@ class hierarchical_predecode3x8_1rw_1r_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(1, "Testing sample for hierarchy_predecode3x8")
a = factory.create(module_type="hierarchical_predecode3x8")
self.local_check(a)
compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py
+3 -2
View File
@@ -8,13 +8,14 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class hierarchical_predecode3x8_pbitcell_test(openram_test):
def runTest(self):
@@ -26,7 +27,7 @@ class hierarchical_predecode3x8_pbitcell_test(openram_test):
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
globals.setup_bitcell()
debug.info(1, "Testing sample for hierarchy_predecode3x8 (multi-port case)")
a = factory.create(module_type="hierarchical_predecode3x8")
self.local_check(a)
compiler/tests/06_hierarchical_predecode4x16_test.py
+1 -1
View File
@@ -23,10 +23,10 @@ class hierarchical_predecode4x16_test(openram_test):
globals.init_openram(config_file)
# Use the 2 port cell since it is usually bigger/easier
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(1, "Testing sample for hierarchy_predecode4x16")
a = factory.create(module_type="hierarchical_predecode4x16")
compiler/tests/07_column_mux_array_1rw_1r_test.py
+2 -2
View File
@@ -25,7 +25,7 @@ class column_mux_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(1, "Testing sample for 2-way column_mux_array port 0")
a = factory.create(module_type="column_mux_array", columns=8, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(a)
@@ -49,7 +49,7 @@ class column_mux_test(openram_test):
debug.info(1, "Testing sample for 8-way column_mux_array port 1")
a = factory.create(module_type="column_mux_array", columns=16, word_size=2, bitcell_bl="bl1", bitcell_br="br1")
self.local_check(a)
globals.end_openram()
compiler/tests/08_precharge_array_1rw_1r_test.py
+4 -3
View File
@@ -8,19 +8,20 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class precharge_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# check precharge array in multi-port
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
@@ -35,7 +36,7 @@ class precharge_1rw_1r_test(openram_test):
debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell (port 1)")
pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0", column_offset=1)
self.local_check(pc)
globals.end_openram()
# run the test from the command line
compiler/tests/08_precharge_array_test.py
+1 -1
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
compiler/tests/08_wordline_buffer_array_test.py
+1 -1
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
compiler/tests/08_wordline_driver_array_1rw_1r_test.py
+1 -1
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
compiler/tests/08_wordline_driver_array_pbitcell_test.py
+1 -1
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
compiler/tests/08_wordline_driver_array_test.py
+1 -1
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
compiler/tests/09_sense_amp_array_1rw_1r_test.py
+2 -1
View File
@@ -8,13 +8,14 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class sense_amp_test(openram_test):
def runTest(self):
compiler/tests/09_sense_amp_array_spare_cols_test.py
+4 -4
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -29,7 +29,7 @@ class sense_amp_array_spare_cols_test(openram_test):
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 and num_spare_cols=2")
a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4, num_spare_cols=2)
self.local_check(a)
# check sense amp array for multi-port
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 1
@@ -44,9 +44,9 @@ class sense_amp_array_spare_cols_test(openram_test):
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4, num_spare_cols=3 (multi-port case)")
a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4, num_spare_cols=3)
self.local_check(a)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/09_sense_amp_array_test.py
+1 -1
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
compiler/tests/10_write_driver_array_1rw_1r_test.py
+2 -1
View File
@@ -8,13 +8,14 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class write_driver_test(openram_test):
def runTest(self):
compiler/tests/10_write_driver_array_pbitcell_test.py
+1 -1
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
compiler/tests/10_write_driver_array_spare_cols_test.py
+3 -3
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -29,7 +29,7 @@ class write_driver_array_spare_cols_test(openram_test):
debug.info(2, "Testing write_driver_array for columns=16, word_size=8 and num_spare_cols=3")
a = factory.create(module_type="write_driver_array", columns=16, word_size=8, num_spare_cols=3)
self.local_check(a)
# check write driver array for multi-port
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 1
@@ -44,7 +44,7 @@ class write_driver_array_spare_cols_test(openram_test):
debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case and num_spare_cols=3")
a = factory.create(module_type="write_driver_array", columns=16, word_size=8, num_spare_cols=3)
self.local_check(a)
globals.end_openram()
# run the test from the command line
compiler/tests/10_write_driver_array_test.py
+1 -1
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
compiler/tests/10_write_mask_and_array_1rw_1r_test.py
+1 -2
View File
@@ -9,7 +9,6 @@
import unittest
from testutils import *
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -27,7 +26,7 @@ class write_mask_and_array_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4")
a = factory.create(module_type="write_mask_and_array", columns=8, word_size=8, write_size=4)
self.local_check(a)
compiler/tests/11_dff_array_test.py
+1 -1
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
compiler/tests/11_dff_buf_array_test.py
+1 -1
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
compiler/tests/12_tri_gate_array_test.py
+6 -4
View File
@@ -8,13 +8,15 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
from sram_factory import factory
import debug
@unittest.skip("SKIPPING 12_tri_gate_array_test")
class tri_gate_array_test(openram_test):
def runTest(self):
@@ -24,13 +26,13 @@ class tri_gate_array_test(openram_test):
debug.info(1, "Testing tri_gate_array for columns=8, word_size=8")
a = factory.create(module_type="tri_gate_array", columns=8, word_size=8)
self.local_check(a)
debug.info(1, "Testing tri_gate_array for columns=16, word_size=8")
a = factory.create(module_type="tri_gate_array", columns=16, word_size=8)
self.local_check(a)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/13_delay_chain_test.py
+2 -2
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -26,7 +26,7 @@ class delay_chain_test(openram_test):
self.local_check(a)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/14_replica_bitcell_array_1rw_1r_test.py
+5 -4
View File
@@ -6,13 +6,14 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class replica_bitcell_array_1rw_1r_test(openram_test):
def runTest(self):
@@ -23,7 +24,7 @@ class replica_bitcell_array_1rw_1r_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Testing 4x4 non-replica array for cell_1rw_1r")
a = factory.create(module_type="replica_bitcell_array",
cols=4,
@@ -38,7 +39,7 @@ class replica_bitcell_array_1rw_1r_test(openram_test):
rbl=[1, 1],
left_rbl=[0])
self.local_check(a)
debug.info(2, "Testing 4x4 array left and right replica for cell_1rw_1r")
a = factory.create(module_type="replica_bitcell_array",
cols=4,
@@ -48,7 +49,7 @@ class replica_bitcell_array_1rw_1r_test(openram_test):
right_rbl=[1])
self.local_check(a)
# Sky 130 has restrictions on the symmetries
if OPTS.tech_name != "sky130":
debug.info(2, "Testing 4x4 array right only replica for cell_1rw_1r")
compiler/tests/14_replica_bitcell_array_test.py
+3 -3
View File
@@ -1,12 +1,12 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2019 Regents of the University of California
# Copyright (c) 2016-2019 Regents of the University of California
# All rights reserved.
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -27,7 +27,7 @@ class replica_bitcell_array_test(openram_test):
debug.info(2, "Testing 4x4 array for bitcell")
a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 0])
self.local_check(a)
globals.end_openram()
# run the test from the command line
compiler/tests/14_replica_column_1rw_1r_test.py
+5 -4
View File
@@ -1,18 +1,19 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2019 Regents of the University of California
# Copyright (c) 2016-2019 Regents of the University of California
# All rights reserved.
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class replica_column_test(openram_test):
def runTest(self):
@@ -31,11 +32,11 @@ class replica_column_test(openram_test):
debug.info(2, "Testing replica column for 6t_cell")
a = factory.create(module_type="replica_column", rows=4, rbl=[1, 1], replica_bit=6)
self.local_check(a)
debug.info(2, "Testing replica column for 6t_cell")
a = factory.create(module_type="replica_column", rows=4, rbl=[2, 0], replica_bit=2)
self.local_check(a)
globals.end_openram()
# run the test from the command line
compiler/tests/14_replica_column_test.py
+8 -7
View File
@@ -1,36 +1,37 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2019 Regents of the University of California
# Copyright (c) 2016-2019 Regents of the University of California
# All rights reserved.
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class replica_column_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(2, "Testing replica column for 6t_cell")
debug.info(2, "Testing replica column for cell_6t")
a = factory.create(module_type="replica_column", rows=4, rbl=[1, 0], replica_bit=1)
self.local_check(a)
debug.info(2, "Testing replica column for 6t_cell")
debug.info(2, "Testing replica column for cell_1rw_1r")
a = factory.create(module_type="replica_column", rows=4, rbl=[1, 1], replica_bit=6)
self.local_check(a)
debug.info(2, "Testing replica column for 6t_cell")
debug.info(2, "Testing replica column for cell_1rw_1r")
a = factory.create(module_type="replica_column", rows=4, rbl=[2, 0], replica_bit=2)
self.local_check(a)
globals.end_openram()
# run the test from the command line
compiler/tests/14_replica_pbitcell_array_test.py
+1 -1
View File
@@ -6,7 +6,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
compiler/tests/15_global_bitcell_array_1rw_1r_test.py
+1 -1
View File
@@ -34,7 +34,7 @@ class global_bitcell_array_test(openram_test):
# debug.info(2, "Testing 4x4 local bitcell array for 6t_cell with replica column")
# a = factory.create(module_type="local_bitcell_array", cols=4, left_rbl=1, rows=4, ports=[0])
# self.local_check(a)
globals.end_openram()
compiler/tests/15_global_bitcell_array_test.py
+1 -1
View File
@@ -29,7 +29,7 @@ class global_bitcell_array_test(openram_test):
debug.info(2, "Testing 2 x 4x4 global bitcell array for 6t_cell")
a = factory.create(module_type="global_bitcell_array", cols=[10, 6], rows=4)
self.local_check(a)
globals.end_openram()
compiler/tests/15_local_bitcell_array_1rw_1r_test.py
+1 -1
View File
@@ -34,7 +34,7 @@ class local_bitcell_array_1rw_1r_test(openram_test):
debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with replica column")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1])
self.local_check(a)
debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with replica column")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0])
self.local_check(a)
compiler/tests/16_control_logic_multiport_test.py
+4 -4
View File
@@ -12,7 +12,7 @@ Run a regression test on a control_logic
import unittest
from testutils import header,openram_test
import sys,os
import sys, os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
@@ -37,13 +37,13 @@ class control_logic_test(openram_test):
debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="rw")
self.local_check(a)
# OPTS.num_rw_ports = 0
# OPTS.num_w_ports = 1
debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="w")
self.local_check(a)
# OPTS.num_w_ports = 0
# OPTS.num_r_ports = 1
debug.info(1, "Testing sample for control_logic for multiport, only read control logic")
@@ -51,7 +51,7 @@ class control_logic_test(openram_test):
self.local_check(a)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/16_control_logic_r_test.py
+1 -1
View File
@@ -27,7 +27,7 @@ class control_logic_test(openram_test):
self.local_check(a)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/16_control_logic_rw_test.py
+2 -2
View File
@@ -25,9 +25,9 @@ class control_logic_test(openram_test):
debug.info(1, "Testing sample for control_logic_rw")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32)
self.local_check(a)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/16_control_logic_w_test.py
+2 -2
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -26,7 +26,7 @@ class control_logic_test(openram_test):
self.local_check(a)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/18_port_address_1rw_1r_test.py
+4 -4
View File
@@ -6,7 +6,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -25,7 +25,7 @@ class port_address_1rw_1r_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(1, "Port address 16 rows")
a = factory.create("port_address", cols=16, rows=16, port=0)
self.local_check(a)
@@ -33,9 +33,9 @@ class port_address_1rw_1r_test(openram_test):
debug.info(1, "Port address 256 rows")
a = factory.create("port_address", cols=256, rows=256, port=1)
self.local_check(a)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/18_port_address_test.py
+3 -3
View File
@@ -6,7 +6,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -23,13 +23,13 @@ class port_address_test(openram_test):
debug.info(1, "Port address 16 rows")
a = factory.create("port_address", cols=16, rows=16, port=0)
self.local_check(a)
debug.info(1, "Port address 512 rows")
a = factory.create("port_address", cols=256, rows=512, port=0)
self.local_check(a)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/18_port_data_1rw_1r_test.py
+4 -4
View File
@@ -6,7 +6,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -25,7 +25,7 @@ class port_data_1rw_1r_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
c = sram_config(word_size=4,
num_words=16)
@@ -68,9 +68,9 @@ class port_data_1rw_1r_test(openram_test):
self.local_check(a)
a = factory.create("port_data", sram_config=c, port=1)
self.local_check(a)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/18_port_data_spare_cols_test.py
+7 -6
View File
@@ -6,13 +6,14 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class port_data_spare_cols_test(openram_test):
def runTest(self):
@@ -57,11 +58,11 @@ class port_data_spare_cols_test(openram_test):
debug.info(1, "Eight way column mux")
a = factory.create("port_data", sram_config=c, port=0)
self.local_check(a)
OPTS.bitcell = "bitcell_1w_1r"
OPTS.num_rw_ports = 0
OPTS.num_r_ports = 1
OPTS.num_w_ports = 1
globals.setup_bitcell()
c.num_words=16
c.words_per_row=1
@@ -72,7 +73,7 @@ class port_data_spare_cols_test(openram_test):
self.local_check(a)
a = factory.create("port_data", sram_config=c, port=1)
self.local_check(a)
c.num_words=32
c.words_per_row=2
factory.reset()
@@ -103,9 +104,9 @@ class port_data_spare_cols_test(openram_test):
self.local_check(a)
a = factory.create("port_data", sram_config=c, port=1)
self.local_check(a)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/18_port_data_test.py
+3 -3
View File
@@ -6,7 +6,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -54,9 +54,9 @@ class port_data_test(openram_test):
debug.info(1, "Eight way column mux")
a = factory.create("port_data", sram_config=c, port=0)
self.local_check(a)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/18_port_data_wmask_1rw_1r_test.py
+1 -2
View File
@@ -7,7 +7,6 @@
import unittest
from testutils import *
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -62,10 +61,10 @@ class port_data_wmask_1rw_1r_test(openram_test):
a = factory.create("port_data", sram_config=c, port=0)
self.local_check(a)
OPTS.bitcell = "bitcell_1w_1r"
OPTS.num_rw_ports = 0
OPTS.num_r_ports = 1
OPTS.num_w_ports = 1
globals.setup_bitcell()
c.num_words = 16
c.words_per_row = 1
compiler/tests/18_port_data_wmask_test.py
+1 -1
View File
@@ -57,10 +57,10 @@ class port_data_wmask_test(openram_test):
a = factory.create("port_data", sram_config=c, port=0)
self.local_check(a)
OPTS.bitcell = "bitcell_1w_1r"
OPTS.num_rw_ports = 0
OPTS.num_r_ports = 1
OPTS.num_w_ports = 1
globals.setup_bitcell()
c.num_words = 16
c.words_per_row = 1
compiler/tests/19_bank_select_pbitcell_test.py
+1 -1
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
compiler/tests/19_bank_select_test.py
+1 -1
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
compiler/tests/19_multi_bank_test.py
+3 -3
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -58,9 +58,9 @@ class multi_bank_test(openram_test):
debug.info(1, "Eight way column mux")
a = factory.create("bank", sram_config=c)
self.local_check(a)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/19_pmulti_bank_test.py
+3 -3
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -63,9 +63,9 @@ class multi_bank_test(openram_test):
debug.info(1, "Eight way column mux")
a = factory.create("bank", sram_config=c)
self.local_check(a)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/19_psingle_bank_test.py
+11 -10
View File
@@ -8,39 +8,40 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 19_psingle_bank_test")
class psingle_bank_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
OPTS.dummy_bitcell="dummy_pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
globals.setup_bitcell()
c = sram_config(word_size=4,
num_words=16)
c.words_per_row=1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
c.num_words=32
c.words_per_row=2
factory.reset()
@@ -48,7 +49,7 @@ class psingle_bank_test(openram_test):
debug.info(1, "Two way column mux")
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
c.num_words=64
c.words_per_row=4
factory.reset()
@@ -56,7 +57,7 @@ class psingle_bank_test(openram_test):
debug.info(1, "Four way column mux")
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
c.word_size=2
c.num_words=128
c.words_per_row=8
@@ -65,9 +66,9 @@ class psingle_bank_test(openram_test):
debug.info(1, "Four way column mux")
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/19_single_bank_1rw_1r_test.py
+3 -3
View File
@@ -27,7 +27,7 @@ class single_bank_1rw_1r_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
c = sram_config(word_size=4,
num_words=16)
@@ -62,9 +62,9 @@ class single_bank_1rw_1r_test(openram_test):
debug.info(1, "Eight way column mux")
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/19_single_bank_1w_1r_test.py
+5 -4
View File
@@ -8,13 +8,14 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class single_bank_1w_1r_test(openram_test):
def runTest(self):
@@ -26,7 +27,7 @@ class single_bank_1w_1r_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 1
globals.setup_bitcell()
c = sram_config(word_size=4,
num_words=16)
@@ -61,9 +62,9 @@ class single_bank_1w_1r_test(openram_test):
debug.info(1, "Eight way column mux")
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/19_single_bank_global_bitline.py
+2 -2
View File
@@ -63,9 +63,9 @@ class single_bank_1rw_1r_test(openram_test):
debug.info(1, "Eight way column mux")
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/19_single_bank_spare_cols_test.py
+3 -3
View File
@@ -8,7 +8,7 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@@ -57,9 +57,9 @@ class single_bank_spare_cols_test(openram_test):
debug.info(1, "Eight way column mux")
a = factory.create("bank", sram_config=c)
self.local_check(a)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
compiler/tests/19_single_bank_test.py
+4 -3
View File
@@ -8,13 +8,14 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class single_bank_test(openram_test):
def runTest(self):
@@ -56,9 +57,9 @@ class single_bank_test(openram_test):
debug.info(1, "Eight way column mux")
a = factory.create("bank", sram_config=c)
self.local_check(a)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()

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