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https://github.com/VLSIDA/OpenRAM.git
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PR from mithro + other changable GDS file names
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+7
-2
@@ -188,6 +188,9 @@ def init_openram(config_file, is_unit_test=True):
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if is_unit_test and CHECKPOINT_OPTS:
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OPTS.__dict__ = CHECKPOINT_OPTS.__dict__.copy()
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return
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# Setup the correct bitcell names
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setup_bitcell()
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# Import these to find the executables for checkpointing
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import characterizer
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@@ -202,8 +205,6 @@ def setup_bitcell():
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"""
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Determine the correct custom or parameterized bitcell for the design.
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"""
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global OPTS
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# If we have non-1rw ports,
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# and the user didn't over-ride the bitcell manually,
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# figure out the right bitcell to use
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@@ -211,8 +212,11 @@ def setup_bitcell():
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if (OPTS.num_rw_ports == 1 and OPTS.num_w_ports == 0 and OPTS.num_r_ports == 0):
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OPTS.bitcell = "bitcell"
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OPTS.bitcell_name = "cell_6t"
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OPTS.replica_bitcell = "replica_bitcell"
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OPTS.replica_bitcell_name = "replica_cell_6t"
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OPTS.dummy_bitcell = "dummy_bitcell"
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OPTS.dummy_bitcell_name = "dummy_cell_6t"
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else:
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ports = ""
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if OPTS.num_rw_ports > 0:
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@@ -225,6 +229,7 @@ def setup_bitcell():
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if ports != "":
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OPTS.bitcell_suffix = "_" + ports
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OPTS.bitcell = "bitcell" + OPTS.bitcell_suffix
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OPTS.bitcell_name = "cell" + OPTS.bitcell_suffix
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# See if bitcell exists
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try:
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