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PR from mithro + other changable GDS file names

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This commit is contained in:
mrg
2020-11-02 16:00:16 -08:00
parent 1caecf5a69
commit fa89b73ef8
38 changed files with 275 additions and 330 deletions
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compiler/bitcells/bitcell.py
+10 -32
View File
@@ -6,9 +6,8 @@
# All rights reserved.
#
import debug
import utils
from tech import GDS, layer
from tech import cell_properties as props
from globals import OPTS
import bitcell_base
@@ -20,41 +19,20 @@ class bitcell(bitcell_base.bitcell_base):
library.
"""
name = "cell_6t"
pin_names = [
props.bitcell.cell_6t.pin.bl,
props.bitcell.cell_6t.pin.br,
props.bitcell.cell_6t.pin.wl,
props.bitcell.cell_6t.pin.vdd,
props.bitcell.cell_6t.pin.gnd,
]
# If we have a split WL bitcell, if not be backwards
# compatible in the tech file
pin_names = [props.bitcell.cell_6t.pin.bl,
props.bitcell.cell_6t.pin.br,
props.bitcell.cell_6t.pin.wl,
props.bitcell.cell_6t.pin.vdd,
props.bitcell.cell_6t.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
storage_nets = ['Q', 'Q_bar']
cell_size_layer = "boundary"
def __init__(self, name=""):
if not name:
name = self.name
bitcell_base.bitcell_base.__init__(self, name)
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.bitcell_name
bitcell_base.bitcell_base.__init__(self, name, cell_name)
debug.info(2, "Create bitcell")
(width, height) = utils.get_libcell_size(name,
GDS["unit"],
layer[self.cell_size_layer])
pin_map = utils.get_libcell_pins(self.pin_names,
name,
GDS["unit"])
self.width = width
self.height = height
self.pin_map = pin_map
self.add_pin_types(self.type_list)
self.nets_match = self.do_nets_exist(self.storage_nets)
def get_all_wl_names(self):
compiler/bitcells/bitcell_1rw_1r.py
+7 -17
View File
@@ -6,11 +6,9 @@
# All rights reserved.
#
import debug
import utils
from tech import GDS, layer, parameter, drc
from tech import cell_properties as props
import logical_effort
import bitcell_base
from globals import OPTS
class bitcell_1rw_1r(bitcell_base.bitcell_base):
@@ -29,27 +27,19 @@ class bitcell_1rw_1r(bitcell_base.bitcell_base):
props.bitcell.cell_1rw1r.pin.wl1,
props.bitcell.cell_1rw1r.pin.vdd,
props.bitcell.cell_1rw1r.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT",
"INPUT", "INPUT", "POWER", "GROUND"]
storage_nets = ['Q', 'Q_bar']
(width, height) = utils.get_libcell_size("cell_1rw_1r",
GDS["unit"],
layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "cell_1rw_1r", GDS["unit"])
def __init__(self, name=""):
# Ignore the name argument
bitcell_base.bitcell_base.__init__(self, "cell_1rw_1r")
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.bitcell_name
bitcell_base.bitcell_base.__init__(self, name, cell_name)
debug.info(2, "Create bitcell with 1RW and 1R Port")
self.width = bitcell_1rw_1r.width
self.height = bitcell_1rw_1r.height
self.pin_map = bitcell_1rw_1r.pin_map
self.add_pin_types(self.type_list)
self.nets_match = self.do_nets_exist(self.storage_nets)
pin_names = bitcell_1rw_1r.pin_names
pin_names = self.pin_names
self.bl_names = [pin_names[0], pin_names[2]]
self.br_names = [pin_names[1], pin_names[3]]
self.wl_names = [pin_names[4], pin_names[5]]
compiler/bitcells/bitcell_1w_1r.py
+7 -16
View File
@@ -6,10 +6,9 @@
# All rights reserved.
#
import debug
import utils
from tech import GDS, layer
from tech import cell_properties as props
import bitcell_base
from globals import OPTS
class bitcell_1w_1r(bitcell_base.bitcell_base):
@@ -31,28 +30,20 @@ class bitcell_1w_1r(bitcell_base.bitcell_base):
type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT",
"INPUT", "INPUT", "POWER", "GROUND"]
storage_nets = ['Q', 'Q_bar']
(width, height) = utils.get_libcell_size("cell_1w_1r",
GDS["unit"],
layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "cell_1w_1r", GDS["unit"])
def __init__(self, name=""):
# Ignore the name argument
bitcell_base.bitcell_base.__init__(self, "cell_1w_1r")
def __init__(self, name, cell_name):
if not cell_name:
cell_name = OPTS.bitcell_name
bitcell_base.bitcell_base.__init__(self, name, cell_name)
debug.info(2, "Create bitcell with 1W and 1R Port")
self.width = bitcell_1w_1r.width
self.height = bitcell_1w_1r.height
self.pin_map = bitcell_1w_1r.pin_map
self.add_pin_types(self.type_list)
self.nets_match = self.do_nets_exist(self.storage_nets)
pin_names = bitcell_1w_1r.pin_names
pin_names = self.pin_names
self.bl_names = [pin_names[0], pin_names[2]]
self.br_names = [pin_names[1], pin_names[3]]
self.wl_names = [pin_names[4], pin_names[5]]
def get_bitcell_pins(self, col, row):
"""
Creates a list of connections in the bitcell,
compiler/bitcells/bitcell_base.py
+15 -3
View File
@@ -8,18 +8,30 @@
import debug
import design
import utils
from globals import OPTS
import logical_effort
from tech import parameter, drc, layer
from tech import GDS, parameter, drc, layer
class bitcell_base(design.design):
"""
Base bitcell parameters to be over-riden.
"""
def __init__(self, name):
design.design.__init__(self, name)
cell_size_layer = "boundary"
def __init__(self, name, cell_name, hard_cell=True):
design.design.__init__(self, name, cell_name)
if hard_cell:
(self.width, self.height) = utils.get_libcell_size(cell_name,
GDS["unit"],
layer[self.cell_size_layer])
self.pin_map = utils.get_libcell_pins(self.pin_names,
cell_name,
GDS["unit"])
self.add_pin_types(self.type_list)
def get_stage_effort(self, load):
parasitic_delay = 1
# This accounts for bitline being drained
compiler/bitcells/col_cap_bitcell_1rw_1r.py
+3 -17
View File
@@ -6,8 +6,6 @@
# All rights reserved.
#
import debug
import utils
from tech import GDS, layer
from tech import cell_properties as props
import bitcell_base
@@ -21,24 +19,12 @@ class col_cap_bitcell_1rw_1r(bitcell_base.bitcell_base):
props.bitcell.cell_1rw1r.pin.bl1,
props.bitcell.cell_1rw1r.pin.br1,
props.bitcell.cell_1rw1r.pin.vdd]
type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT",
"POWER", "GROUND"]
(width, height) = utils.get_libcell_size("col_cap_cell_1rw_1r",
GDS["unit"],
layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names,
"col_cap_cell_1rw_1r",
GDS["unit"])
def __init__(self, name=""):
def __init__(self, name="col_cap_cell_1rw_1r"):
# Ignore the name argument
bitcell_base.bitcell_base.__init__(self, "col_cap_cell_1rw_1r")
bitcell_base.bitcell_base.__init__(self, name)
debug.info(2, "Create col_cap bitcell 1rw+1r object")
self.width = col_cap_bitcell_1rw_1r.width
self.height = col_cap_bitcell_1rw_1r.height
self.pin_map = col_cap_bitcell_1rw_1r.pin_map
self.add_pin_types(self.type_list)
self.no_instances = True
compiler/bitcells/dummy_bitcell.py
+7 -15
View File
@@ -6,10 +6,9 @@
# All rights reserved.
#
import debug
import utils
from tech import GDS, layer
from tech import cell_properties as props
import bitcell_base
from globals import OPTS
class dummy_bitcell(bitcell_base.bitcell_base):
@@ -24,19 +23,12 @@ class dummy_bitcell(bitcell_base.bitcell_base):
props.bitcell.cell_6t.pin.wl,
props.bitcell.cell_6t.pin.vdd,
props.bitcell.cell_6t.pin.gnd]
(width, height) = utils.get_libcell_size("dummy_cell_6t",
GDS["unit"],
layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "dummy_cell_6t", GDS["unit"])
def __init__(self, name=""):
# Ignore the name argument
bitcell_base.bitcell_base.__init__(self, "dummy_cell_6t")
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.dummy_bitcell_name
bitcell_base.bitcell_base.__init__(self, name, cell_name)
debug.info(2, "Create dummy bitcell")
self.width = dummy_bitcell.width
self.height = dummy_bitcell.height
self.pin_map = dummy_bitcell.pin_map
compiler/bitcells/dummy_bitcell_1rw_1r.py
+5 -16
View File
@@ -6,10 +6,9 @@
# All rights reserved.
#
import debug
import utils
from tech import GDS, layer
from tech import cell_properties as props
import bitcell_base
from globals import OPTS
class dummy_bitcell_1rw_1r(bitcell_base.bitcell_base):
@@ -27,23 +26,13 @@ class dummy_bitcell_1rw_1r(bitcell_base.bitcell_base):
props.bitcell.cell_1rw1r.pin.wl1,
props.bitcell.cell_1rw1r.pin.vdd,
props.bitcell.cell_1rw1r.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT",
"INPUT", "INPUT", "POWER", "GROUND"]
(width, height) = utils.get_libcell_size("dummy_cell_1rw_1r",
GDS["unit"],
layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names,
"dummy_cell_1rw_1r",
GDS["unit"])
def __init__(self, name=""):
# Ignore the name argument
bitcell_base.bitcell_base.__init__(self, "dummy_cell_1rw_1r")
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.dummy_bitcell_name
bitcell_base.bitcell_base.__init__(self, name, cell_name)
debug.info(2, "Create dummy bitcell 1rw+1r object")
self.width = dummy_bitcell_1rw_1r.width
self.height = dummy_bitcell_1rw_1r.height
self.pin_map = dummy_bitcell_1rw_1r.pin_map
self.add_pin_types(self.type_list)
compiler/bitcells/dummy_bitcell_1w_1r.py
+6 -15
View File
@@ -6,10 +6,9 @@
# All rights reserved.
#
import debug
import utils
from tech import GDS, layer
from tech import cell_properties as props
import bitcell_base
from globals import OPTS
class dummy_bitcell_1w_1r(bitcell_base.bitcell_base):
@@ -29,21 +28,13 @@ class dummy_bitcell_1w_1r(bitcell_base.bitcell_base):
props.bitcell.cell_1w1r.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT",
"INPUT", "INPUT", "POWER", "GROUND"]
(width, height) = utils.get_libcell_size("dummy_cell_1w_1r",
GDS["unit"],
layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names,
"dummy_cell_1w_1r",
GDS["unit"])
def __init__(self, name=""):
# Ignore the name argument
bitcell_base.bitcell_base.__init__(self, "dummy_cell_1w_1r")
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.dummy_bitcell_name
bitcell_base.bitcell_base.__init__(self, name, cell_name)
debug.info(2, "Create dummy bitcell 1w+1r object")
self.width = dummy_bitcell_1w_1r.width
self.height = dummy_bitcell_1w_1r.height
self.pin_map = dummy_bitcell_1w_1r.pin_map
self.add_pin_types(self.type_list)
compiler/bitcells/dummy_pbitcell.py
+8 -7
View File
@@ -7,11 +7,11 @@
#
import debug
import design
from tech import drc, spice,parameter
from vector import vector
from globals import OPTS
from sram_factory import factory
class dummy_pbitcell(design.design):
"""
Creates a replica bitcell using pbitcell
@@ -23,7 +23,7 @@ class dummy_pbitcell(design.design):
self.num_r_ports = OPTS.num_r_ports
self.total_ports = self.num_rw_ports + self.num_w_ports + self.num_r_ports
design.design.__init__(self, name)
design.design.__init__(self, name, name)
debug.info(1, "create a dummy bitcell using pbitcell with {0} rw ports, {1} w ports and {2} r ports".format(self.num_rw_ports,
self.num_w_ports,
self.num_r_ports))
@@ -54,7 +54,8 @@ class dummy_pbitcell(design.design):
self.add_pin("gnd")
def add_modules(self):
self.prbc = factory.create(module_type="pbitcell",dummy_bitcell=True)
self.prbc = factory.create(module_type="pbitcell",
dummy_bitcell=True)
self.add_mod(self.prbc)
self.height = self.prbc.height
@@ -69,20 +70,20 @@ class dummy_pbitcell(design.design):
temp.append("bl{}".format(port))
temp.append("br{}".format(port))
for port in range(self.total_ports):
temp.append("wl{}".format(port))
temp.append("wl{}".format(port))
temp.append("vdd")
temp.append("gnd")
self.connect_inst(temp)
def place_pbitcell(self):
self.prbc_inst.place(offset=vector(0,0))
self.prbc_inst.place(offset=vector(0, 0))
def route_rbc_connections(self):
def route_rbc_connections(self):
for port in range(self.total_ports):
self.copy_layout_pin(self.prbc_inst, "bl{}".format(port))
self.copy_layout_pin(self.prbc_inst, "br{}".format(port))
for port in range(self.total_ports):
self.copy_layout_pin(self.prbc_inst, "wl{}".format(port))
self.copy_layout_pin(self.prbc_inst, "wl{}".format(port))
self.copy_layout_pin(self.prbc_inst, "vdd")
self.copy_layout_pin(self.prbc_inst, "gnd")
compiler/bitcells/pbitcell.py
+1 -1
View File
@@ -30,7 +30,7 @@ class pbitcell(bitcell_base.bitcell_base):
self.replica_bitcell = replica_bitcell
self.dummy_bitcell = dummy_bitcell
bitcell_base.bitcell_base.__init__(self, name)
bitcell_base.bitcell_base.__init__(self, name, name, hard_cell=False)
fmt_str = "{0} rw ports, {1} w ports and {2} r ports"
info_string = fmt_str.format(self.num_rw_ports,
self.num_w_ports,
compiler/bitcells/replica_bitcell.py
+15 -16
View File
@@ -8,11 +8,11 @@
import design
import debug
import utils
from tech import GDS,layer,drc,parameter,cell_properties
from tech import GDS, layer
from tech import cell_properties as props
from globals import OPTS
class replica_bitcell(design.design):
"""
A single bit cell (6T, 8T, etc.)
@@ -26,24 +26,23 @@ class replica_bitcell(design.design):
props.bitcell.cell_6t.pin.vdd,
props.bitcell.cell_6t.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
cell_size_layer = "boundary"
if not OPTS.netlist_only:
(width,height) = utils.get_libcell_size("replica_cell_6t", GDS["unit"], layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "replica_cell_6t", GDS["unit"])
else:
(width,height) = (0,0)
pin_map = []
def __init__(self, name=""):
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.replica_bitcell_name
# Ignore the name argument
design.design.__init__(self, "replica_cell_6t")
design.design.__init__(self, name, cell_name)
debug.info(2, "Create replica bitcell object")
self.width = replica_bitcell.width
self.height = replica_bitcell.height
self.pin_map = replica_bitcell.pin_map
self.add_pin_types(self.type_list)
(self.width, self.height) = utils.get_libcell_size(cell_name,
GDS["unit"],
layer[self.cell_size_layer])
self.pin_map = utils.get_libcell_pins(self.pin_names,
cell_name,
GDS["unit"])
def get_stage_effort(self, load):
parasitic_delay = 1
size = 0.5 #This accounts for bitline being drained thought the access TX and internal node
compiler/bitcells/replica_bitcell_1rw_1r.py
+7 -14
View File
@@ -7,9 +7,9 @@
#
import design
import debug
import utils
from tech import GDS,layer,drc,parameter
from tech import cell_properties as props
from globals import OPTS
class replica_bitcell_1rw_1r(design.design):
"""
@@ -26,21 +26,14 @@ class replica_bitcell_1rw_1r(design.design):
props.bitcell.cell_1rw1r.pin.wl1,
props.bitcell.cell_1rw1r.pin.vdd,
props.bitcell.cell_1rw1r.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]
type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]
(width,height) = utils.get_libcell_size("replica_cell_1rw_1r", GDS["unit"], layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "replica_cell_1rw_1r", GDS["unit"])
def __init__(self, name=""):
# Ignore the name argument
design.design.__init__(self, "replica_cell_1rw_1r")
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.replica_bitcell_name
design.design.__init__(self, name, cell_name)
debug.info(2, "Create replica bitcell 1rw+1r object")
self.width = replica_bitcell_1rw_1r.width
self.height = replica_bitcell_1rw_1r.height
self.pin_map = replica_bitcell_1rw_1r.pin_map
self.add_pin_types(self.type_list)
def get_stage_effort(self, load):
parasitic_delay = 1
size = 0.5 #This accounts for bitline being drained thought the access TX and internal node
compiler/bitcells/replica_bitcell_1w_1r.py
+7 -14
View File
@@ -7,9 +7,9 @@
#
import design
import debug
import utils
from tech import GDS,layer,drc,parameter
from tech import cell_properties as props
from globals import OPTS
class replica_bitcell_1w_1r(design.design):
"""
@@ -26,21 +26,14 @@ class replica_bitcell_1w_1r(design.design):
props.bitcell.cell_1w1r.pin.wl1,
props.bitcell.cell_1w1r.pin.vdd,
props.bitcell.cell_1w1r.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "INPUT", "INPUT", "POWER", "GROUND"]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "INPUT", "INPUT", "POWER", "GROUND"]
(width,height) = utils.get_libcell_size("replica_cell_1w_1r", GDS["unit"], layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "replica_cell_1w_1r", GDS["unit"])
def __init__(self, name=""):
# Ignore the name argument
design.design.__init__(self, "replica_cell_1w_1r")
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.replica_bitcell_name
design.design.__init__(self, name, cell_name)
debug.info(2, "Create replica bitcell 1w+1r object")
self.width = replica_bitcell_1w_1r.width
self.height = replica_bitcell_1w_1r.height
self.pin_map = replica_bitcell_1w_1r.pin_map
self.add_pin_types(self.type_list)
def get_stage_effort(self, load):
parasitic_delay = 1
size = 0.5 #This accounts for bitline being drained thought the access TX and internal node
compiler/bitcells/replica_pbitcell.py
+8 -7
View File
@@ -7,11 +7,11 @@
#
import debug
import design
from tech import drc, spice,parameter
from vector import vector
from globals import OPTS
from sram_factory import factory
class replica_pbitcell(design.design):
"""
Creates a replica bitcell using pbitcell
@@ -23,7 +23,7 @@ class replica_pbitcell(design.design):
self.num_r_ports = OPTS.num_r_ports
self.total_ports = self.num_rw_ports + self.num_w_ports + self.num_r_ports
design.design.__init__(self, name)
design.design.__init__(self, name, name)
debug.info(1, "create a replica bitcell using pbitcell with {0} rw ports, {1} w ports and {2} r ports".format(self.num_rw_ports,
self.num_w_ports,
self.num_r_ports))
@@ -54,7 +54,8 @@ class replica_pbitcell(design.design):
self.add_pin("gnd")
def add_modules(self):
self.prbc = factory.create(module_type="pbitcell",replica_bitcell=True)
self.prbc = factory.create(module_type="pbitcell",
replica_bitcell=True)
self.add_mod(self.prbc)
self.height = self.prbc.height
@@ -69,20 +70,20 @@ class replica_pbitcell(design.design):
temp.append("bl{}".format(port))
temp.append("br{}".format(port))
for port in range(self.total_ports):
temp.append("wl{}".format(port))
temp.append("wl{}".format(port))
temp.append("vdd")
temp.append("gnd")
self.connect_inst(temp)
def place_pbitcell(self):
self.prbc_inst.place(offset=vector(0,0))
self.prbc_inst.place(offset=vector(0, 0))
def route_rbc_connections(self):
def route_rbc_connections(self):
for port in range(self.total_ports):
self.copy_layout_pin(self.prbc_inst, "bl{}".format(port))
self.copy_layout_pin(self.prbc_inst, "br{}".format(port))
for port in range(self.total_ports):
self.copy_layout_pin(self.prbc_inst, "wl{}".format(port))
self.copy_layout_pin(self.prbc_inst, "wl{}".format(port))
self.copy_layout_pin(self.prbc_inst, "vdd")
self.copy_layout_pin(self.prbc_inst, "gnd")
compiler/bitcells/row_cap_bitcell_1rw_1r.py
+2 -16
View File
@@ -6,8 +6,6 @@
# All rights reserved.
#
import debug
import utils
from tech import GDS, layer
from tech import cell_properties as props
import bitcell_base
@@ -22,23 +20,11 @@ class row_cap_bitcell_1rw_1r(bitcell_base.bitcell_base):
pin_names = [props.bitcell.cell_1rw1r.pin.wl0,
props.bitcell.cell_1rw1r.pin.wl1,
props.bitcell.cell_1rw1r.pin.gnd]
type_list = ["INPUT", "INPUT", "GROUND"]
(width, height) = utils.get_libcell_size("row_cap_cell_1rw_1r",
GDS["unit"],
layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names,
"row_cap_cell_1rw_1r",
GDS["unit"])
def __init__(self, name=""):
def __init__(self, name="row_cap_cell_1rw_1r"):
# Ignore the name argument
bitcell_base.bitcell_base.__init__(self, "row_cap_cell_1rw_1r")
bitcell_base.bitcell_base.__init__(self, name)
debug.info(2, "Create row_cap bitcell 1rw+1r object")
self.width = row_cap_bitcell_1rw_1r.width
self.height = row_cap_bitcell_1rw_1r.height
self.pin_map = row_cap_bitcell_1rw_1r.pin_map
self.add_pin_types(self.type_list)
self.no_instances = True