mirror of https://github.com/VLSIDA/OpenRAM.git
Fix ALL of the indents.
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37fffb2ed2
commit
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@ -43,7 +43,7 @@ class psram_1bank_4mux_func_test(openram_test):
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num_banks=1)
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num_banks=1)
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c.words_per_row=4
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c.words_per_row=4
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c.recompute_sizes()
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c.recompute_sizes()
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debug.info(1, "Functional test for {}rw,{}r,{}w psram with"
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debug.info(1, "Functional test for {}rw,{}r,{}w psram with"
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"{} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
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"{} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
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OPTS.num_r_ports,
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OPTS.num_r_ports,
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OPTS.num_w_ports,
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OPTS.num_w_ports,
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@ -43,7 +43,7 @@ class psram_1bank_8mux_func_test(openram_test):
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num_banks=1)
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num_banks=1)
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c.words_per_row=8
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c.words_per_row=8
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c.recompute_sizes()
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c.recompute_sizes()
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debug.info(1, "Functional test for {}rw,{}r,{}w psram with"
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debug.info(1, "Functional test for {}rw,{}r,{}w psram with"
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"{} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
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"{} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
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OPTS.num_r_ports,
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OPTS.num_r_ports,
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OPTS.num_w_ports,
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OPTS.num_w_ports,
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@ -41,10 +41,11 @@ class psram_1bank_nomux_func_test(openram_test):
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num_banks=1)
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num_banks=1)
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c.words_per_row=1
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c.words_per_row=1
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c.recompute_sizes()
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c.recompute_sizes()
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debug.info(1, "Functional test for sram 1rw,1r with {} bit words, {} words, {} words per row, {} banks".format(c.word_size,
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debug.info(1, "Functional test for sram 1rw,1r with "
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c.num_words,
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"{} bit words, {} words, {} words per row, {} banks".format(c.word_size,
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c.words_per_row,
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c.num_words,
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c.num_banks))
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c.words_per_row,
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c.num_banks))
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s = factory.create(module_type="sram", sram_config=c)
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s = factory.create(module_type="sram", sram_config=c)
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tempspice = OPTS.openram_temp + "sram.sp"
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tempspice = OPTS.openram_temp + "sram.sp"
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s.sp_write(tempspice)
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s.sp_write(tempspice)
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@ -36,11 +36,12 @@ class sram_wmask_func_test(openram_test):
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num_banks=1)
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num_banks=1)
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c.words_per_row=1
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c.words_per_row=1
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c.recompute_sizes()
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c.recompute_sizes()
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debug.info(1, "Functional test for sram with {} bit words, {} words, {} words per row, {} bit writes, {} banks".format(c.word_size,
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debug.info(1, "Functional test for sram with "
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c.num_words,
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"{} bit words, {} words, {} words per row, {} bit writes, {} banks".format(c.word_size,
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c.words_per_row,
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c.num_words,
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c.write_size,
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c.words_per_row,
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c.num_banks))
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c.write_size,
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c.num_banks))
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s = factory.create(module_type="sram", sram_config=c)
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s = factory.create(module_type="sram", sram_config=c)
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tempspice = OPTS.openram_temp + "sram.sp"
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tempspice = OPTS.openram_temp + "sram.sp"
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s.sp_write(tempspice)
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s.sp_write(tempspice)
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