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Initial commit of sky130 config files
This commit is contained in:
mrg
@@ -0,0 +1,37 @@
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#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California
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# All rights reserved.
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#
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import debug
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from tech import cell_properties as props
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import bitcell_base
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class sky130_bitcell(bitcell_base.bitcell_base):
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"""
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A single bit cell (6T, 8T, etc.) This module implements the
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single memory cell used in the design. It is a hand-made cell, so
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the layout and netlist should be available in the technology
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library.
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"""
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def __init__(self, version="opt1", name=""):
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if version == "opt1":
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cell_name = "sky130_fd_bd_sram__sram_sp_cell_opt1"
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elif version == "opt1a":
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cell_name = "sky130_fd_bd_sram__sram_sp_cell_opt1a"
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else:
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debug.error("Invalid sky130 cell name", -1)
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super().__init__(name, cell_name=cell_name, prop=props.bitcell_1port)
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debug.info(2, "Create bitcell")
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def build_graph(self, graph, inst_name, port_nets):
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"""
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Adds edges based on inputs/outputs.
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Overrides base class function.
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"""
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self.add_graph_edges(graph, port_nets)
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@@ -0,0 +1,93 @@
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#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California
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# All rights reserved.
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#
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import debug
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from bitcell_array import bitcell_array
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from sky130_bitcell_base_array import sky130_bitcell_base_array
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from globals import OPTS
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from sram_factory import factory
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class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
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"""
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Creates a rows x cols array of memory cells.
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Assumes bit-lines and word lines are connected by abutment.
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"""
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def __init__(self, rows, cols, column_offset=0, name=""):
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# Don't call the regular bitcell_array constructor since we don't want its constructor, just
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# some of it's useful member functions
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sky130_bitcell_base_array.__init__(self, rows=rows, cols=cols, column_offset=column_offset, name=name)
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if self.row_size % 2 == 0:
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debug.error("Invalid number of rows {}. number of rows (excluding dummy rows) must be odd to connect to col ends".format(self.row_size), -1)
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debug.info(1, "Creating {0} {1} x {2}".format(self.name, self.row_size, self.column_size))
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self.add_comment("rows: {0} cols: {1}".format(self.row_size, self.column_size))
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# This will create a default set of bitline/wordline names
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self.create_all_bitline_names()
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self.create_all_wordline_names()
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def add_modules(self):
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""" Add the modules used in this design """
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# Bitcell for port names only
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self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
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self.add_mod(self.cell)
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self.cell2 = factory.create(module_type=OPTS.bitcell, version="opt1a")
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self.add_mod(self.cell2)
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self.strap = factory.create(module_type="internal", version="wlstrap")
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self.add_mod(self.strap)
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self.strap2 = factory.create(module_type="internal", version="wlstrap_p")
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self.add_mod(self.strap2)
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self.strap3 = factory.create(module_type="internal", version="wlstrapa")
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self.add_mod(self.strap3)
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def create_instances(self):
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""" Create the module instances used in this design """
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self.cell_inst = {}
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self.array_layout = []
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alternate_bitcell = (self.row_size) % 2
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for row in range(0, self.row_size):
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row_layout = []
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alternate_strap = (self.row_size+1) % 2
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for col in range(0, self.column_size):
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if alternate_bitcell == 1:
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row_layout.append(self.cell)
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self.cell_inst[row, col]=self.add_inst(name="row_{}_col_{}_bitcell".format(row, col),
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mod=self.cell)
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else:
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row_layout.append(self.cell2)
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self.cell_inst[row, col]=self.add_inst(name="row_{}_col_{}_bitcell".format(row, col),
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mod=self.cell2)
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self.connect_inst(self.get_bitcell_pins(row, col))
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if col != self.column_size - 1:
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if alternate_strap:
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row_layout.append(self.strap2)
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self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col),
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mod=self.strap2)
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alternate_strap = 0
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else:
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if row % 2:
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row_layout.append(self.strap3)
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self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col),
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mod=self.strap3)
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else:
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row_layout.append(self.strap)
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self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col),
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mod=self.strap)
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alternate_strap = 1
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self.connect_inst(self.get_strap_pins(row, col))
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if alternate_bitcell == 0:
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alternate_bitcell = 1
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else:
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alternate_bitcell = 0
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self.array_layout.append(row_layout)
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@@ -0,0 +1,147 @@
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#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California
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# All rights reserved.
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#
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import debug
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import geometry
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from sram_factory import factory
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from bitcell_base_array import bitcell_base_array
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from globals import OPTS
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from tech import layer
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class sky130_bitcell_base_array(bitcell_base_array):
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"""
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Abstract base class for bitcell-arrays -- bitcell, dummy, replica
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"""
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def __init__(self, name, rows, cols, column_offset):
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super().__init__(name, rows, cols, column_offset)
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debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
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self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
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def place_array(self, name_template, row_offset=0, col_offset=0):
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yoffset = 0.0
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for row in range(0, len(self.array_layout)):
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xoffset = 0.0
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for col in range(0, len(self.array_layout[row])):
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self.place_inst = self.insts[(col) + (row) * len(self.array_layout[row])]
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if row % 2 == 0:
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if col == 0:
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self.place_inst.place(offset=[xoffset, yoffset + self.cell.height], mirror="MX")
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elif col % 4 == 0:
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self.place_inst.place(offset=[xoffset, yoffset + self.cell.height], mirror="MX")
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elif col % 4 == 3 :
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self.place_inst.place(offset=[xoffset, yoffset + self.cell.height], mirror="MX")
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elif col % 4 == 2:
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self.place_inst.place(offset=[xoffset + self.cell.width, yoffset + self.cell.height], mirror="XY")
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else:
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self.place_inst.place(offset=[xoffset, yoffset + self.cell.height], mirror="MX")
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else:
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if col == 0:
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self.place_inst.place(offset=[xoffset, yoffset])
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elif col % 4 == 0:
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self.place_inst.place(offset=[xoffset, yoffset])
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elif col % 4 == 3 :
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self.place_inst.place(offset=[xoffset, yoffset])
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elif col % 4 == 2:
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self.place_inst.place(offset=[xoffset + self.cell.width, yoffset], mirror="MY")
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# self.place_inst.place(offset=[xoffset, yoffset])
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else:
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self.place_inst.place(offset=[xoffset, yoffset])
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xoffset += self.place_inst.width
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yoffset += self.place_inst.height
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self.width = max([x.rx() for x in self.insts])
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self.height = max([x.uy() for x in self.insts])
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def get_bitcell_pins(self, row, col):
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"""
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Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array
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"""
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bitcell_pins = []
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for port in self.all_ports:
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bitcell_pins.extend([x for x in self.get_bitline_names(port) if x.endswith("_{0}".format(col))])
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bitcell_pins.append("gnd") # gnd
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bitcell_pins.append("vdd") # vdd
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bitcell_pins.append("vdd") # vpb
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bitcell_pins.append("gnd") # vnb
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bitcell_pins.extend([x for x in self.all_wordline_names if x.endswith("_{0}".format(row))])
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return bitcell_pins
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def get_strap_pins(self, row, col):
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"""
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Creates a list of connections in the strap cell,
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indexed by column and row, for instance use in bitcell_array
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"""
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strap_pins = ["vdd"]
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return strap_pins
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def get_col_cap_pins(self, row, col):
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"""
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"""
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strap_pins = ["gnd", "gnd", "vdd"]
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return strap_pins
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def get_col_cap_p_pins(self, row, col):
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"""
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"""
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strap_pins = []
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for port in self.all_ports:
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strap_pins.extend([x for x in self.get_bitline_names(port) if "bl" in x and x.endswith("_{0}".format(col))])
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strap_pins.extend(["vdd", "gnd"])
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for port in self.all_ports:
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strap_pins.extend([x for x in self.get_bitline_names(port) if "br" in x and x.endswith("_{0}".format(col))])
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return strap_pins
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def get_row_cap_pins(self, row, col):
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"""
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"""
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strap_pins = ["gnd", "vdd", "gnd"]
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return strap_pins
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def get_corner_pins(self):
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"""
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"""
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strap_pins = ["vdd", "gnd", "vdd"]
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return strap_pins
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def add_supply_pins(self):
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""" Add the layout pins """
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# Copy a vdd/gnd layout pin from every cell
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vdd", "gnd"]:
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self.copy_layout_pin(inst, pin_name)
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if row == 2: #add only 1 label per col
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if 'VPB' in self.cell_inst[row, col].mod.pins:
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pin = inst.get_pin("vpb")
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self.objs.append(geometry.rectangle(layer["nwell"],
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pin.ll(),
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pin.width(),
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pin.height()))
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self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
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if 'VNB' in self.cell_inst[row, col].mod.pins:
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try:
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from tech import layer_override
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if layer_override['VNB']:
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pin = inst.get_pin("vnb")
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self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
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self.objs.append(geometry.rectangle(layer["pwellp"],
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pin.ll(),
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pin.width(),
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pin.height()))
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except:
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pin = inst.get_pin("vnb")
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self.add_label("vdd", pin.layer, pin.center())
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@@ -0,0 +1,36 @@
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#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California
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# All rights reserved.
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#
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import debug
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import design
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from tech import cell_properties as props
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class sky130_col_cap(design.design):
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def __init__(self, version, name=""):
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if version == "colend":
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cell_name = "sky130_fd_bd_sram__sram_sp_colend"
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prop = props.col_cap_1port_bitcell
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elif version == "colend_p_cent":
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cell_name = "sky130_fd_bd_sram__sram_sp_colend_p_cent"
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prop = props.col_cap_1port_strap_ground
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elif version == "colenda":
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cell_name = "sky130_fd_bd_sram__sram_sp_colenda"
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prop = props.col_cap_1port_bitcell
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elif version == "colenda_p_cent":
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cell_name = "sky130_fd_bd_sram__sram_sp_colenda_p_cent"
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prop = props.col_cap_1port_strap_ground
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elif version == "colend_cent":
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cell_name = "sky130_fd_bd_sram__sram_sp_colend_cent"
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prop = props.col_cap_1port_strap_power
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elif version == "colenda_cent":
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cell_name = "sky130_fd_bd_sram__sram_sp_colenda_cent"
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prop = props.col_cap_1port_strap_power
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else:
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debug.error("Invalid type for col_end", -1)
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super().__init__(name=name, cell_name=cell_name, prop=prop)
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@@ -0,0 +1,185 @@
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#!/usr/bin/env python3
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# See LICENSE for licensing information.
|
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#
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# Copyright (c) 2016-2021 Regents of the University of California
|
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# All rights reserved.
|
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#
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from sram_factory import factory
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from sky130_bitcell_base_array import sky130_bitcell_base_array
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from globals import OPTS
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class sky130_col_cap_array(sky130_bitcell_base_array):
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"""
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Generate a dummy row/column for the replica array.
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"""
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def __init__(self, rows, cols, location, column_offset=0, mirror=0, name=""):
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# Don't call the regular col-cap_array constructor since we don't want its constructor, just
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# some of it's useful member functions
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sky130_bitcell_base_array.__init__(self, rows=rows, cols=cols, column_offset=column_offset, name=name)
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self.mirror = mirror
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self.location = location
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self.rows = rows
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self.cols = cols
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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""" Create and connect the netlist """
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# This module has no wordlines
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# self.create_all_wordline_names()
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# This module has no bitlines
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# self.create_all_bitline_names()
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self.add_modules()
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self.create_all_wordline_names()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place_array("dummy_r{0}_c{1}", self.mirror)
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_modules(self):
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""" Add the modules used in this design """
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if self.location == "top":
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self.colend1 = factory.create(module_type="col_cap", version="colend")
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self.add_mod(self.colend1)
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self.colend2 = factory.create(module_type="col_cap", version="colend_p_cent")
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self.add_mod(self.colend2)
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self.colend3 = factory.create(module_type="col_cap", version="colend_cent")
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self.add_mod(self.colend3)
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elif self.location == "bottom":
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self.colend1 = factory.create(module_type="col_cap", version="colenda")
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self.add_mod(self.colend1)
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self.colend2 = factory.create(module_type="col_cap", version="colenda_p_cent")
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self.add_mod(self.colend2)
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self.colend3 = factory.create(module_type="col_cap", version="colenda_cent")
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self.add_mod(self.colend3)
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self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
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|
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def create_instances(self):
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""" Create the module instances used in this design """
|
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self.cell_inst = {}
|
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self.array_layout = []
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bitline = 0
|
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for col in range((self.column_size * 2) - 1):
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row_layout = []
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name="rca_{0}_{1}".format(self.location, col)
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# Top/bottom cell are always dummy cells.
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# Regular array cells are replica cells (>left_rbl and <rows-right_rbl)
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# Replic bit specifies which other bit (in the full range (0,rows) to make a replica cell.
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pins = []
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if col % 4 == 0:
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row_layout.append(self.colend1)
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self.cell_inst[col]=self.add_inst(name=name, mod=self.colend1)
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pins.append("fake_bl_{}".format(bitline))
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pins.append("vdd")
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pins.append("gnd")
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pins.append("fake_br_{}".format(bitline))
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bitline += 1
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elif col % 4 == 1:
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row_layout.append(self.colend2)
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self.cell_inst[col]=self.add_inst(name=name, mod=self.colend3)
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pins.append("vdd")
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pins.append("vdd")
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pins.append("gnd")
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elif col % 4 == 2:
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row_layout.append(self.colend1)
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self.cell_inst[col]=self.add_inst(name=name, mod=self.colend1)
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pins.append("fake_bl_{}".format(bitline))
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pins.append("vdd")
|
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pins.append("gnd")
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pins.append("fake_br_{}".format(bitline))
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bitline += 1
|
||||
elif col % 4 ==3:
|
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row_layout.append(self.colend2)
|
||||
self.cell_inst[col]=self.add_inst(name=name, mod=self.colend2)
|
||||
pins.append("gnd")
|
||||
pins.append("vdd")
|
||||
pins.append("gnd")
|
||||
|
||||
self.connect_inst(pins)
|
||||
|
||||
self.array_layout.append(row_layout)
|
||||
|
||||
def place_array(self, name_template, row_offset=0):
|
||||
xoffset = 0.0
|
||||
yoffset = 0.0
|
||||
|
||||
for col in range(len(self.insts)):
|
||||
inst = self.insts[col]
|
||||
if col % 4 == 0:
|
||||
inst.place(offset=[xoffset + inst.width, yoffset], mirror="MY")
|
||||
elif col % 4 == 1:
|
||||
inst.place(offset=[xoffset, yoffset])
|
||||
elif col % 4 == 2:
|
||||
inst.place(offset=[xoffset, yoffset])
|
||||
elif col % 4 ==3:
|
||||
inst.place(offset=[xoffset, yoffset])
|
||||
|
||||
xoffset += inst.width
|
||||
|
||||
self.width = max([x.rx() for x in self.insts])
|
||||
self.height = max([x.uy() for x in self.insts])
|
||||
|
||||
def add_pins(self):
|
||||
|
||||
for fake_bl in range(self.cols):
|
||||
self.add_pin("fake_bl_{}".format(fake_bl), "OUTPUT")
|
||||
self.add_pin("fake_br_{}".format(fake_bl), "OUTPUT")
|
||||
self.add_pin("fake_wl", "INPUT")
|
||||
self.add_pin("vdd", "POWER")
|
||||
self.add_pin("gnd", "GROUND")
|
||||
|
||||
def add_layout_pins(self):
|
||||
""" Add the layout pins """
|
||||
# Add vdd/gnd via stacks
|
||||
for cols in range((self.column_size * 2) - 1):
|
||||
inst = self.cell_inst[cols]
|
||||
for pin_name in ["vdd", "gnd"]:
|
||||
for pin in inst.get_pins(pin_name):
|
||||
if inst.mod.cell_name == 'sky130_fd_bd_sram__sram_sp_colend' or 'sky130_fd_bd_sram__sram_sp_colenda':
|
||||
if inst.mirror == "MY":
|
||||
if pin_name == "vdd":
|
||||
self.add_layout_pin_rect_center(text="vdd",
|
||||
layer=pin.layer,
|
||||
offset=inst.lr(),
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
elif pin_name == "gnd":
|
||||
self.add_layout_pin_rect_center(text="gnd",
|
||||
layer=pin.layer,
|
||||
offset=inst.ll(),
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
else:
|
||||
if pin_name == "vdd":
|
||||
self.add_layout_pin_rect_center(text="vdd",
|
||||
layer=pin.layer,
|
||||
offset=inst.ll(),
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
elif pin_name == "gnd":
|
||||
self.add_layout_pin_rect_center(text="gnd",
|
||||
layer=pin.layer,
|
||||
offset=inst.lr(),
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
return
|
||||
|
||||
def create_all_wordline_names(self, row_size=None):
|
||||
if row_size == None:
|
||||
row_size = self.row_size
|
||||
|
||||
for row in range(row_size):
|
||||
for port in self.all_ports:
|
||||
self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
|
||||
|
||||
self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl]
|
||||
@@ -0,0 +1,33 @@
|
||||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
import debug
|
||||
import design
|
||||
import utils
|
||||
from tech import layer, GDS
|
||||
|
||||
|
||||
class sky130_corner(design.design):
|
||||
|
||||
def __init__(self, location, name=""):
|
||||
super().__init__(name)
|
||||
|
||||
if location == "ul":
|
||||
self.name = "sky130_fd_bd_sram__sram_sp_corner"
|
||||
elif location == "ur":
|
||||
self.name = "sky130_fd_bd_sram__sram_sp_cornerb"
|
||||
elif location == "ll":
|
||||
self.name = "sky130_fd_bd_sram__sram_sp_cornera"
|
||||
elif location == "lr":
|
||||
self.name = "sky130_fd_bd_sram__sram_sp_cornera"
|
||||
else:
|
||||
debug.error("Invalid sky130_corner location", -1)
|
||||
design.design.__init__(self, name=self.name)
|
||||
(self.width, self.height) = utils.get_libcell_size(self.name,
|
||||
GDS["unit"],
|
||||
layer["mem"])
|
||||
# pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"])
|
||||
@@ -0,0 +1,153 @@
|
||||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
from sky130_bitcell_base_array import sky130_bitcell_base_array
|
||||
from sram_factory import factory
|
||||
from globals import OPTS
|
||||
|
||||
|
||||
class sky130_dummy_array(sky130_bitcell_base_array):
|
||||
"""
|
||||
Generate a dummy row/column for the replica array.
|
||||
"""
|
||||
def __init__(self, rows, cols, column_offset=0, row_offset=0 ,mirror=0, location="", name=""):
|
||||
|
||||
super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
|
||||
self.mirror = mirror
|
||||
|
||||
self.create_netlist()
|
||||
if not OPTS.netlist_only:
|
||||
self.create_layout()
|
||||
|
||||
def create_netlist(self):
|
||||
""" Create and connect the netlist """
|
||||
# This will create a default set of bitline/wordline names
|
||||
self.create_all_bitline_names()
|
||||
self.create_all_wordline_names()
|
||||
|
||||
self.add_modules()
|
||||
self.add_pins()
|
||||
self.create_instances()
|
||||
|
||||
def create_layout(self):
|
||||
self.place_array("dummy_r{0}_c{1}", self.mirror)
|
||||
|
||||
self.add_layout_pins()
|
||||
|
||||
self.add_boundary()
|
||||
|
||||
self.DRC_LVS()
|
||||
|
||||
def add_modules(self):
|
||||
""" Add the modules used in this design """
|
||||
self.dummy_cell = factory.create(module_type=OPTS.dummy_bitcell, version="opt1")
|
||||
self.add_mod(self.dummy_cell)
|
||||
self.dummy_cell2 = factory.create(module_type=OPTS.dummy_bitcell, version="opt1a")
|
||||
self.add_mod(self.dummy_cell2)
|
||||
self.strap = factory.create(module_type="internal", version="wlstrap")
|
||||
self.add_mod(self.strap)
|
||||
self.strap2 = factory.create(module_type="internal", version="wlstrap_p")
|
||||
self.add_mod(self.strap2)
|
||||
self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
|
||||
|
||||
def create_instances(self):
|
||||
""" Create the module instances used in this design """
|
||||
self.cell_inst = {}
|
||||
self.array_layout = []
|
||||
alternate_bitcell = (self.row_size + 1) % 2
|
||||
for row in range(0, self.row_size):
|
||||
|
||||
row_layout = []
|
||||
|
||||
alternate_strap = (self.row_size + 1) % 2
|
||||
for col in range(0, self.column_size):
|
||||
if alternate_bitcell == 1:
|
||||
row_layout.append(self.dummy_cell)
|
||||
self.cell_inst[row, col]=self.add_inst(name="row_{}_col_{}_bitcell".format(row, col),
|
||||
mod=self.dummy_cell)
|
||||
else:
|
||||
row_layout.append(self.dummy_cell2)
|
||||
self.cell_inst[row, col]=self.add_inst(name="row_{}_col_{}_bitcell".format(row, col),
|
||||
mod=self.dummy_cell2)
|
||||
|
||||
self.connect_inst(self.get_bitcell_pins(row, col))
|
||||
if col != self.column_size - 1:
|
||||
if alternate_strap:
|
||||
row_layout.append(self.strap2)
|
||||
self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col),
|
||||
mod=self.strap2)
|
||||
alternate_strap = 0
|
||||
else:
|
||||
|
||||
row_layout.append(self.strap)
|
||||
self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col),
|
||||
mod=self.strap)
|
||||
alternate_strap = 1
|
||||
self.connect_inst(self.get_strap_pins(row, col))
|
||||
if alternate_bitcell == 0:
|
||||
alternate_bitcell = 1
|
||||
else:
|
||||
alternate_bitcell = 0
|
||||
self.array_layout.append(row_layout)
|
||||
|
||||
def add_pins(self):
|
||||
# bitline pins are not added because they are floating
|
||||
for wl_name in self.get_wordline_names():
|
||||
self.add_pin(wl_name, "INPUT")
|
||||
for bl in range(self.column_size):
|
||||
self.add_pin("dummy_bl_{}".format(bl))
|
||||
self.add_pin("dummy_br_{}".format(bl))
|
||||
self.add_pin("vdd", "POWER")
|
||||
self.add_pin("gnd", "GROUND")
|
||||
|
||||
def add_layout_pins(self):
|
||||
""" Add the layout pins """
|
||||
bitline_names = self.cell.get_all_bitline_names()
|
||||
for col in range(self.column_size):
|
||||
for port in self.all_ports:
|
||||
bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
|
||||
self.add_layout_pin(text="bl_{0}_{1}".format(port, col),
|
||||
layer=bl_pin.layer,
|
||||
offset=bl_pin.ll().scale(1, 0),
|
||||
width=bl_pin.width(),
|
||||
height=self.height)
|
||||
br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
|
||||
self.add_layout_pin(text="br_{0}_{1}".format(port, col),
|
||||
layer=br_pin.layer,
|
||||
offset=br_pin.ll().scale(1, 0),
|
||||
width=br_pin.width(),
|
||||
height=self.height)
|
||||
# self.add_rect(layer=bl_pin.layer,
|
||||
# offset=bl_pin.ll().scale(1, 0),
|
||||
# width=bl_pin.width(),
|
||||
# height=self.height)
|
||||
# self.add_rect(layer=br_pin.layer,
|
||||
# offset=br_pin.ll().scale(1, 0),
|
||||
# width=br_pin.width(),
|
||||
# height=self.height)
|
||||
|
||||
wl_names = self.cell.get_all_wl_names()
|
||||
for row in range(self.row_size):
|
||||
for port in self.all_ports:
|
||||
wl_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
|
||||
self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
|
||||
layer=wl_pin.layer,
|
||||
offset=wl_pin.ll().scale(0, 1),
|
||||
width=self.width,
|
||||
height=wl_pin.height())
|
||||
|
||||
# Copy a vdd/gnd layout pin from every cell
|
||||
for row in range(self.row_size):
|
||||
for col in range(self.column_size):
|
||||
inst = self.cell_inst[row, col]
|
||||
for pin_name in ["vdd", "gnd"]:
|
||||
self.copy_layout_pin(inst, pin_name)
|
||||
|
||||
def input_load(self):
|
||||
# FIXME: This appears to be old code from previous characterization. Needs to be updated.
|
||||
wl_wire = self.gen_wl_wire()
|
||||
return wl_wire.return_input_cap()
|
||||
@@ -0,0 +1,28 @@
|
||||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
import debug
|
||||
from tech import cell_properties as props
|
||||
import bitcell_base
|
||||
|
||||
|
||||
class sky130_dummy_bitcell(bitcell_base.bitcell_base):
|
||||
"""
|
||||
A single bit cell (6T, 8T, etc.) This module implements the
|
||||
single memory cell used in the design. It is a hand-made cell, so
|
||||
the layout and netlist should be available in the technology
|
||||
library.
|
||||
"""
|
||||
def __init__(self, version, name=""):
|
||||
# Ignore the name argument
|
||||
|
||||
if version == "opt1":
|
||||
cell_name = "sky130_fd_bd_sram__openram_sp_cell_opt1_dummy"
|
||||
elif version == "opt1a":
|
||||
cell_name = "sky130_fd_bd_sram__openram_sp_cell_opt1a_dummy"
|
||||
super().__init__(name, cell_name, prop=props.bitcell_1port)
|
||||
debug.info(2, "Create dummy bitcell")
|
||||
@@ -0,0 +1,31 @@
|
||||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
import debug
|
||||
import design
|
||||
import utils
|
||||
from tech import layer, GDS
|
||||
|
||||
|
||||
class sky130_internal(design.design):
|
||||
|
||||
def __init__(self, version, name=""):
|
||||
super().__init__(name)
|
||||
|
||||
if version == "wlstrap":
|
||||
self.name = "sky130_fd_bd_sram__sram_sp_wlstrap"
|
||||
elif version == "wlstrap_p":
|
||||
self.name = "sky130_fd_bd_sram__sram_sp_wlstrap_p"
|
||||
elif version == "wlstrapa":
|
||||
self.name = "sky130_fd_bd_sram__sram_sp_wlstrapa"
|
||||
else:
|
||||
debug.error("Invalid version", -1)
|
||||
design.design.__init__(self, name=self.name)
|
||||
(self.width, self.height) = utils.get_libcell_size(self.name,
|
||||
GDS["unit"],
|
||||
layer["mem"])
|
||||
# pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"])
|
||||
@@ -0,0 +1,54 @@
|
||||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
import debug
|
||||
import bitcell_base
|
||||
from tech import parameter, drc
|
||||
from tech import cell_properties as props
|
||||
import logical_effort
|
||||
|
||||
|
||||
class sky130_replica_bitcell(bitcell_base.bitcell_base):
|
||||
"""
|
||||
A single bit cell (6T, 8T, etc.)
|
||||
This module implements the single memory cell used in the design. It
|
||||
is a hand-made cell, so the layout and netlist should be available in
|
||||
the technology library. """
|
||||
|
||||
def __init__(self, version, name=""):
|
||||
if version == "opt1":
|
||||
cell_name = "sky130_fd_bd_sram__openram_sp_cell_opt1_replica"
|
||||
elif version == "opt1a":
|
||||
cell_name = "sky130_fd_bd_sram__openram_sp_cell_opt1a_replica"
|
||||
super().__init__(name, cell_name, prop=props.bitcell_1port)
|
||||
debug.info(2, "Create replica bitcell object")
|
||||
|
||||
def get_stage_effort(self, load):
|
||||
parasitic_delay = 1
|
||||
size = 0.5 # This accounts for bitline being drained thought the access TX and internal node
|
||||
cin = 3 # Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
|
||||
read_port_load = 0.5 # min size NMOS gate load
|
||||
return logical_effort.logical_effort('bitline', size, cin, load + read_port_load, parasitic_delay, False)
|
||||
|
||||
def input_load(self):
|
||||
"""Return the relative capacitance of the access transistor gates"""
|
||||
|
||||
# FIXME: This applies to bitline capacitances as well.
|
||||
access_tx_cin = parameter["6T_access_size"] / drc["minwidth_tx"]
|
||||
return 2 * access_tx_cin
|
||||
|
||||
def analytical_power(self, corner, load):
|
||||
"""Bitcell power in nW. Only characterizes leakage."""
|
||||
from tech import spice
|
||||
leakage = spice["bitcell_leakage"]
|
||||
dynamic = 0 # temporary
|
||||
total_power = self.return_power(dynamic, leakage)
|
||||
return total_power
|
||||
|
||||
def build_graph(self, graph, inst_name, port_nets):
|
||||
"""Adds edges based on inputs/outputs. Overrides base class function."""
|
||||
self.add_graph_edges(graph, port_nets)
|
||||
@@ -0,0 +1,340 @@
|
||||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
import debug
|
||||
from replica_bitcell_array import replica_bitcell_array
|
||||
from vector import vector
|
||||
from sky130_bitcell_base_array import sky130_bitcell_base_array
|
||||
from utils import round_to_grid
|
||||
from math import sqrt
|
||||
from tech import drc
|
||||
from tech import array_row_multiple
|
||||
from tech import array_col_multiple
|
||||
from globals import OPTS
|
||||
|
||||
|
||||
class sky130_replica_bitcell_array(replica_bitcell_array, sky130_bitcell_base_array):
|
||||
"""
|
||||
Creates a bitcell arrow of cols x rows and then adds the replica
|
||||
and dummy columns and rows. Replica columns are on the left and
|
||||
right, respectively and connected to the given bitcell ports.
|
||||
Dummy are the outside columns/rows with WL and BL tied to gnd.
|
||||
Requires a regular bitcell array, replica bitcell, and dummy
|
||||
bitcell (Bl/BR disconnected).
|
||||
"""
|
||||
def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""):
|
||||
total_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
|
||||
self.all_ports = list(range(total_ports))
|
||||
|
||||
self.column_size = cols
|
||||
self.row_size = rows
|
||||
|
||||
# This is how many RBLs are in all the arrays
|
||||
if rbl:
|
||||
self.rbl = rbl
|
||||
else:
|
||||
self.rbl=[1, 1 if len(self.all_ports)>1 else 0]
|
||||
# This specifies which RBL to put on the left or right
|
||||
# by port number
|
||||
# This could be an empty list
|
||||
if left_rbl != None:
|
||||
self.left_rbl = left_rbl
|
||||
else:
|
||||
self.left_rbl = [0]
|
||||
# This could be an empty list
|
||||
if right_rbl != None:
|
||||
self.right_rbl = right_rbl
|
||||
else:
|
||||
self.right_rbl=[1] if len(self.all_ports) > 1 else []
|
||||
self.rbls = self.left_rbl + self.right_rbl
|
||||
|
||||
if ((self.column_size + self.rbl[0] + self.rbl[1]) % array_col_multiple != 0):
|
||||
debug.error("Invalid number of cols including rbl(s): {}. Total cols must be divisible by {}".format(self.column_size + self.rbl[0] + self.rbl[1], array_col_multiple), -1)
|
||||
|
||||
if ((self.row_size + self.rbl[0] + self.rbl[1]) % array_row_multiple != 0):
|
||||
debug.error("invalid number of rows including dummy row(s): {}. Total cols must be divisible by {}".format(self.row_size + self.rbl[0] + self.rbl[1], array_row_multiple), -15)
|
||||
|
||||
super().__init__(self.row_size, self.column_size, rbl, left_rbl, right_rbl, name)
|
||||
|
||||
def create_layout(self):
|
||||
# We will need unused wordlines grounded, so we need to know their layer
|
||||
# and create a space on the left and right for the vias to connect to ground
|
||||
pin = self.cell.get_pin(self.cell.get_all_wl_names()[0])
|
||||
pin_layer = pin.layer
|
||||
self.unused_pitch = 1.5 * getattr(self, "{}_pitch".format(pin_layer))
|
||||
self.unused_offset = vector(self.unused_pitch, 0)
|
||||
|
||||
# This is a bitcell x bitcell offset to scale
|
||||
self.bitcell_offset = vector(self.cell.width, self.cell.height)
|
||||
self.strap_offset = vector(self.replica_col_insts[0].mod.strap1.width, self.replica_col_insts[0].mod.strap1.height)
|
||||
self.col_end_offset = vector(self.dummy_row_insts[0].mod.colend1.width, self.dummy_row_insts[0].mod.colend1.height)
|
||||
self.row_end_offset = vector(self.dummy_col_insts[0].mod.rowend1.width, self.dummy_col_insts[0].mod.rowend1.height)
|
||||
|
||||
# Everything is computed with the main array at (self.unused_pitch, 0) to start
|
||||
self.bitcell_array_inst.place(offset=self.unused_offset)
|
||||
|
||||
self.add_replica_columns()
|
||||
|
||||
self.add_end_caps()
|
||||
|
||||
# Array was at (0, 0) but move everything so it is at the lower left
|
||||
self.offset_all_coordinates()
|
||||
|
||||
# Add extra width on the left and right for the unused WLs
|
||||
#self.width = self.dummy_col_insts[0].rx() + self.unused_offset[0]
|
||||
self.width = self.dummy_col_insts[1].rx()
|
||||
self.height = self.dummy_col_insts[0].uy()
|
||||
|
||||
self.add_layout_pins()
|
||||
|
||||
self.route_unused_wordlines()
|
||||
|
||||
self.add_boundary()
|
||||
|
||||
self.DRC_LVS()
|
||||
|
||||
def add_pins(self):
|
||||
super().add_pins()
|
||||
self.add_pin("vpb", "BIAS")
|
||||
self.add_pin("vnb", "BIAS")
|
||||
|
||||
def add_replica_columns(self):
|
||||
""" Add replica columns on left and right of array """
|
||||
|
||||
# Grow from left to right, toward the array
|
||||
for bit, port in enumerate(self.left_rbl):
|
||||
offset = self.bitcell_array_inst.ll() \
|
||||
- vector(0, self.col_cap_bottom.height) \
|
||||
- vector(0, self.dummy_row.height) \
|
||||
- vector(self.replica_columns[0].width, 0)
|
||||
self.replica_col_insts[bit].place(offset + vector(0, self.replica_col_insts[bit].height), mirror="MX")
|
||||
|
||||
# Grow to the right of the bitcell array, array outward
|
||||
for bit, port in enumerate(self.right_rbl):
|
||||
offset = self.bitcell_array_inst.lr() \
|
||||
+ self.bitcell_offset.scale(bit, -self.rbl[0] - (self.col_end_offset.y / self.cell.height)) \
|
||||
+ self.strap_offset.scale(bit, -self.rbl[0] - 1)
|
||||
self.replica_col_insts[self.rbl[0] + bit].place(offset)
|
||||
|
||||
# Replica dummy rows
|
||||
# Add the dummy rows even if we aren't adding the replica column to this bitcell array
|
||||
# These grow up, toward the array
|
||||
for bit in range(self.rbl[0]):
|
||||
dummy_offset = self.bitcell_offset.scale(0, -self.rbl[0] + bit + (-self.rbl[0] + bit) % 2) + self.unused_offset
|
||||
self.dummy_row_replica_insts[bit].place(offset=dummy_offset,
|
||||
mirror="MX" if (-self.rbl[0] + bit) % 2 else "R0")
|
||||
# These grow up, away from the array
|
||||
for bit in range(self.rbl[1]):
|
||||
dummy_offset = self.bitcell_offset.scale(0, bit + bit % 2) + self.bitcell_array_inst.ul()
|
||||
self.dummy_row_replica_insts[self.rbl[0] + bit].place(offset=dummy_offset,
|
||||
mirror="MX" if bit % 2 else "R0")
|
||||
|
||||
def add_end_caps(self):
|
||||
""" Add dummy cells or end caps around the array """
|
||||
|
||||
dummy_row_offset = self.bitcell_offset.scale(0, self.rbl[1]) + self.bitcell_array_inst.ul()
|
||||
self.dummy_row_insts[1].place(offset=dummy_row_offset)
|
||||
|
||||
dummy_row_offset = self.bitcell_offset.scale(0, -self.rbl[0] - (self.col_end_offset.y / self.cell.height)) + self.unused_offset
|
||||
self.dummy_row_insts[0].place(offset=dummy_row_offset + vector(0, self.dummy_row_insts[0].height), mirror="MX")
|
||||
|
||||
# Far left dummy col
|
||||
# Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
|
||||
dummy_col_offset = self.bitcell_offset.scale(len(self.right_rbl) * (1 + self.strap_offset.x / self.cell.width), -self.rbl[0] - (self.col_end_offset.y / self.cell.height)) - vector(self.replica_col_insts[0].width, 0) + self.unused_offset
|
||||
self.dummy_col_insts[0].place(offset=dummy_col_offset, mirror="MY")
|
||||
|
||||
# Far right dummy col
|
||||
# Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
|
||||
dummy_col_offset = self.bitcell_offset.scale(len(self.right_rbl) * (1 + self.strap_offset.x / self.cell.width), -self.rbl[0] - (self.col_end_offset.y / self.cell.height)) + self.bitcell_array_inst.lr()
|
||||
self.dummy_col_insts[1].place(offset=dummy_col_offset)
|
||||
|
||||
def route_unused_wordlines(self):
|
||||
""" Connect the unused RBL and dummy wordlines to gnd """
|
||||
return
|
||||
# This grounds all the dummy row word lines
|
||||
for inst in self.dummy_row_insts:
|
||||
for wl_name in self.col_cap.get_wordline_names():
|
||||
self.ground_pin(inst, wl_name)
|
||||
|
||||
# Ground the unused replica wordlines
|
||||
for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
|
||||
for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
|
||||
if wl_name in self.gnd_wordline_names:
|
||||
self.ground_pin(inst, pin_name)
|
||||
|
||||
def add_layout_pins(self):
|
||||
""" Add the layout pins """
|
||||
|
||||
for row_end in self.dummy_col_insts:
|
||||
row_end = row_end.mod
|
||||
for (rba_wl_name, wl_name) in zip(self.get_all_wordline_names(), row_end.get_wordline_names()):
|
||||
pin = row_end.get_pin(wl_name)
|
||||
self.add_layout_pin(text=rba_wl_name,
|
||||
layer=pin.layer,
|
||||
offset=vector(0,pin.ll().scale(0, 1)[1]),
|
||||
#width=self.width,
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
|
||||
pin_height = (round_to_grid(drc["minarea_m3"] / round_to_grid(sqrt(drc["minarea_m3"]))) + drc["{0}_to_{0}".format('m3')])
|
||||
drc_width = drc["{0}_to_{0}".format('m3')]
|
||||
|
||||
# vdd/gnd are only connected in the perimeter cells
|
||||
# replica column should only have a vdd/gnd in the dummy cell on top/bottom
|
||||
supply_insts = self.dummy_row_insts + self.replica_col_insts
|
||||
|
||||
for pin_name in self.supplies:
|
||||
for supply_inst in supply_insts:
|
||||
vdd_alternate = 0
|
||||
gnd_alternate = 0
|
||||
for cell_inst in supply_inst.mod.insts:
|
||||
inst = cell_inst.mod
|
||||
for pin in inst.get_pins(pin_name):
|
||||
if pin.name == 'vdd':
|
||||
if vdd_alternate:
|
||||
connection_offset = 0.035
|
||||
vdd_alternate = 0
|
||||
else:
|
||||
connection_offset = -0.035
|
||||
vdd_alternate = 1
|
||||
connection_width = drc["minwidth_{}".format('m1')]
|
||||
track_offset = 1
|
||||
elif pin.name == 'gnd':
|
||||
if gnd_alternate:
|
||||
connection_offset = 0.035
|
||||
gnd_alternate = 0
|
||||
else:
|
||||
connection_offset = -0.035
|
||||
gnd_alternate = 1
|
||||
connection_width = drc["minwidth_{}".format('m1')]
|
||||
track_offset = 4
|
||||
pin_width = round_to_grid(sqrt(drc["minarea_m3"]))
|
||||
pin_height = round_to_grid(drc["minarea_m3"] / pin_width)
|
||||
if inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colend_p_cent' or inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colenda_p_cent' or inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colend_cent' or inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colenda_cent' or 'corner' in inst.cell_name:
|
||||
if 'dummy_row' in supply_inst.name and supply_inst.mirror == 'MX':
|
||||
pin_center = vector(pin.center()[0], -1 * track_offset * (pin_height + drc_width*2))
|
||||
self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset, 0), connection_width)
|
||||
elif 'dummy_row' in supply_inst.name:
|
||||
pin_center = vector(pin.center()[0],inst.height + 1 * track_offset* (pin_height + drc_width*2))
|
||||
self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset, self.height), connection_width)
|
||||
elif 'replica_col' in supply_inst.name and cell_inst.mirror == 'MX':
|
||||
pin_center = vector(pin.center()[0], -1 * track_offset* (pin_height + drc_width*2))
|
||||
self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset, 0), connection_width)
|
||||
elif 'replica_col' in supply_inst.name:
|
||||
pin_center = vector(pin.center()[0],inst.height + 1 * track_offset * (pin_height + drc_width*2))
|
||||
self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset,self.height), connection_width)
|
||||
self.add_via_stack_center(from_layer=pin.layer,
|
||||
to_layer='m2',
|
||||
offset=pin_center+supply_inst.ll()+cell_inst.ll() + vector(connection_offset,0))
|
||||
#self.add_power_pin(name=pin_name,
|
||||
# loc=pin_center+supply_inst.ll()+cell_inst.ll() + vector(connection_offset,0),
|
||||
# start_layer=pin.layer,
|
||||
# end_layer='m2')
|
||||
|
||||
|
||||
# add well contacts to perimeter cells
|
||||
for pin_name in ['vpb', 'vnb']:
|
||||
for supply_inst in supply_insts:
|
||||
vnb_alternate = 0
|
||||
vpb_alternate = 0
|
||||
for cell_inst in supply_inst.mod.insts:
|
||||
|
||||
inst = cell_inst.mod
|
||||
for pin in inst.get_pins(pin_name):
|
||||
if pin.name == 'vpb':
|
||||
if vpb_alternate:
|
||||
connection_offset = 0.01
|
||||
vpb_alternate = 0
|
||||
else:
|
||||
connection_offset = 0.02
|
||||
vpb_alternate = 1
|
||||
connection_width = drc["minwidth_{}".format('m1')]
|
||||
track_offset = 2
|
||||
elif pin.name == 'vnb':
|
||||
if vnb_alternate:
|
||||
connection_offset = -0.01
|
||||
vnb_alternate = 0
|
||||
else:
|
||||
connection_offset = -0.02
|
||||
vnb_alternate = 1
|
||||
connection_width = drc["minwidth_{}".format('m1')]
|
||||
track_offset = 3
|
||||
if inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colend_p_cent' or inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colenda_p_cent' or inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colend_cent' or inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colenda_cent':
|
||||
if 'dummy_row' in supply_inst.name and supply_inst.mirror == 'MX':
|
||||
pin_center = vector(pin.center()[0], -1 * track_offset * (pin_height + drc_width*2))
|
||||
self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset, 0), connection_width)
|
||||
elif 'dummy_row' in supply_inst.name:
|
||||
pin_center = vector(pin.center()[0],inst.height + 1 * track_offset* (pin_height + drc_width*2))
|
||||
self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset, self.height), connection_width)
|
||||
elif 'replica_col' in supply_inst.name and cell_inst.mirror == 'MX':
|
||||
pin_center = vector(pin.center()[0], -1 * track_offset* (pin_height + drc_width*2))
|
||||
self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset, 0), connection_width)
|
||||
elif 'replica_col' in supply_inst.name:
|
||||
pin_center = vector(pin.center()[0],inst.height + 1 * track_offset * (pin_height + drc_width*2))
|
||||
self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset,self.height), connection_width)
|
||||
self.add_via_stack_center(from_layer=pin.layer,
|
||||
to_layer='m2',
|
||||
offset=pin_center+supply_inst.ll()+cell_inst.ll() + vector(connection_offset,0))
|
||||
#self.add_power_pin(name=pin_name,
|
||||
# loc=pin_center+supply_inst.ll()+cell_inst.ll() + vector(connection_offset,0),
|
||||
# start_layer=pin.layer)
|
||||
|
||||
min_area = drc["minarea_{}".format('m3')]
|
||||
for track,supply, offset in zip(range(1,5),['vdd','vpb','vnb','gnd'],[min_area * 6,min_area * 6, 0, 0]):
|
||||
y_offset = track * (pin_height + drc_width*2)
|
||||
self.add_segment_center('m2', vector(0,-y_offset), vector(self.width, -y_offset), drc["minwidth_{}".format('m2')])
|
||||
self.add_segment_center('m2', vector(0,self.height + y_offset), vector(self.width, self.height + y_offset), drc["minwidth_{}".format('m2')])
|
||||
self.add_power_pin(name=supply,
|
||||
loc=vector(round_to_grid(sqrt(min_area))/2 + offset, -y_offset),
|
||||
start_layer='m2')
|
||||
self.add_power_pin(name=supply,
|
||||
loc=vector(round_to_grid(sqrt(min_area))/2 + offset, self.height + y_offset),
|
||||
start_layer='m2')
|
||||
self.add_power_pin(name=supply,
|
||||
loc=vector(self.width - round_to_grid(sqrt(min_area))/2 - offset, -y_offset),
|
||||
start_layer='m2')
|
||||
self.add_power_pin(name=supply,
|
||||
loc=vector(self.width - round_to_grid(sqrt(min_area))/2 - offset, self.height + y_offset),
|
||||
start_layer='m2')
|
||||
|
||||
self.offset_all_coordinates()
|
||||
self.height = self.height + self.dummy_col_insts[0].lr().y * 2
|
||||
|
||||
for pin_name in self.all_bitline_names:
|
||||
pin_list = self.bitcell_array_inst.get_pins(pin_name)
|
||||
for pin in pin_list:
|
||||
if 'bl' in pin.name:
|
||||
self.add_layout_pin(text=pin_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1, 0),
|
||||
width=pin.width(),
|
||||
height=self.height)
|
||||
elif 'br' in pin_name:
|
||||
self.add_layout_pin(text=pin_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1, 0) + vector(0,pin_height + drc_width*2),
|
||||
width=pin.width(),
|
||||
height=self.height - 2 *(pin_height + drc_width*2))
|
||||
# Replica bitlines
|
||||
if len(self.rbls) > 0:
|
||||
for (names, inst) in zip(self.rbl_bitline_names, self.replica_col_insts):
|
||||
pin_names = self.replica_columns[self.rbls[0]].all_bitline_names
|
||||
for (bl_name, pin_name) in zip(names, pin_names):
|
||||
pin = inst.get_pin(pin_name)
|
||||
if 'rbl_bl' in bl_name:
|
||||
self.add_layout_pin(text=bl_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1, 0),
|
||||
width=pin.width(),
|
||||
height=self.height)
|
||||
elif 'rbl_br' in bl_name:
|
||||
self.add_layout_pin(text=bl_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1, 0) + vector(0,(pin_height + drc_width*2)),
|
||||
width=pin.width(),
|
||||
height=self.height - 2 *(pin_height + drc_width*2))
|
||||
return
|
||||
@@ -0,0 +1,261 @@
|
||||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
import debug
|
||||
from sky130_bitcell_base_array import sky130_bitcell_base_array
|
||||
from sram_factory import factory
|
||||
from globals import OPTS
|
||||
import geometry
|
||||
from tech import layer
|
||||
|
||||
|
||||
class sky130_replica_column(sky130_bitcell_base_array):
|
||||
"""
|
||||
Generate a replica bitline column for the replica array.
|
||||
Rows is the total number of rows i the main array.
|
||||
rbl is a tuple with the number of left and right replica bitlines.
|
||||
Replica bit specifies which replica column this is (to determine where to put the
|
||||
replica cell relative to the bottom (including the dummy bit at 0).
|
||||
"""
|
||||
|
||||
def __init__(self, name, rows, rbl, replica_bit, column_offset=0):
|
||||
# Used for pin names and properties
|
||||
self.cell = factory.create(module_type=OPTS.bitcell)
|
||||
# Row size is the number of rows with word lines
|
||||
self.row_size = sum(rbl) + rows
|
||||
# Start of regular word line rows
|
||||
self.row_start = rbl[0] + 1
|
||||
# End of regular word line rows
|
||||
self.row_end = self.row_start + rows
|
||||
if not self.cell.end_caps:
|
||||
self.row_size += 2
|
||||
super().__init__(rows=self.row_size, cols=1, column_offset=column_offset, name=name)
|
||||
|
||||
self.rows = rows
|
||||
self.left_rbl = rbl[0]
|
||||
self.right_rbl = rbl[1]
|
||||
self.replica_bit = replica_bit
|
||||
# left, right, regular rows plus top/bottom dummy cells
|
||||
|
||||
self.total_size = self.left_rbl + rows + self.right_rbl + 2
|
||||
self.column_offset = column_offset
|
||||
|
||||
if self.rows % 2 == 0:
|
||||
debug.error("Invalid number of rows {}. Number of rows must be even to connect to col ends".format(self.rows), -1)
|
||||
if self.column_offset % 2 == 0:
|
||||
debug.error("Invalid column_offset {}. Column offset must be odd to connect to col ends".format(self.rows), -1)
|
||||
debug.check(replica_bit != 0 and replica_bit != rows,
|
||||
"Replica bit cannot be the dummy row.")
|
||||
debug.check(replica_bit <= self.left_rbl or replica_bit >= self.total_size - self.right_rbl - 1,
|
||||
"Replica bit cannot be in the regular array.")
|
||||
# if OPTS.tech_name == "sky130":
|
||||
# debug.check(rows % 2 == 0 and (self.left_rbl + 1) % 2 == 0,
|
||||
# "sky130 currently requires rows to be even and to start with X mirroring"
|
||||
# + " (left_rbl must be even) for LVS.")
|
||||
# commented out to support odd row counts while testing opc
|
||||
|
||||
self.create_netlist()
|
||||
if not OPTS.netlist_only:
|
||||
self.create_layout()
|
||||
|
||||
def create_netlist(self):
|
||||
self.add_modules()
|
||||
self.add_pins()
|
||||
self.create_instances()
|
||||
|
||||
def create_layout(self):
|
||||
self.place_instances()
|
||||
|
||||
self.width = max([x.rx() for x in self.insts])
|
||||
self.height = max([x.uy() for x in self.insts])
|
||||
|
||||
self.add_layout_pins()
|
||||
|
||||
self.add_boundary()
|
||||
self.DRC_LVS()
|
||||
|
||||
def add_pins(self):
|
||||
|
||||
self.create_all_bitline_names()
|
||||
self.create_all_wordline_names(self.row_size+2)
|
||||
# +2 to add fake wl pins for colends
|
||||
|
||||
self.add_pin_list(self.all_bitline_names, "OUTPUT")
|
||||
self.add_pin_list(self.all_wordline_names, "INPUT")
|
||||
|
||||
self.add_pin("vdd", "POWER")
|
||||
self.add_pin("gnd", "GROUND")
|
||||
|
||||
def add_modules(self):
|
||||
self.replica_cell = factory.create(module_type="replica_bitcell_1port", version="opt1")
|
||||
self.add_mod(self.replica_cell)
|
||||
self.cell = self.replica_cell
|
||||
self.replica_cell2 = factory.create(module_type="replica_bitcell_1port", version="opt1a")
|
||||
self.add_mod(self.replica_cell2)
|
||||
|
||||
self.dummy_cell = factory.create(module_type="dummy_bitcell_1port", version="opt1")
|
||||
self.dummy_cell2 = factory.create(module_type="dummy_bitcell_1port", version="opt1")
|
||||
|
||||
self.strap1 = factory.create(module_type="internal", version="wlstrap")
|
||||
self.add_mod(self.strap1)
|
||||
self.strap2 = factory.create(module_type="internal", version="wlstrap_p")
|
||||
self.add_mod(self.strap2)
|
||||
|
||||
self.colend = factory.create(module_type="col_cap", version="colend")
|
||||
self.edge_cell = self.colend
|
||||
self.add_mod(self.colend)
|
||||
self.colenda = factory.create(module_type="col_cap", version="colenda")
|
||||
self.add_mod(self.colenda)
|
||||
self.colend_p_cent = factory.create(module_type="col_cap", version="colend_p_cent")
|
||||
self.add_mod(self.colend_p_cent)
|
||||
self.colenda_p_cent = factory.create(module_type="col_cap", version="colenda_p_cent")
|
||||
self.add_mod(self.colenda_p_cent)
|
||||
|
||||
def create_instances(self):
|
||||
self.cell_inst = {}
|
||||
self.array_layout = []
|
||||
alternate_bitcell = (self.rows + 1) % 2
|
||||
for row in range(self.total_size):
|
||||
row_layout = []
|
||||
name="rbc_{0}".format(row)
|
||||
# Top/bottom cell are always dummy cells.
|
||||
# Regular array cells are replica cells (>left_rbl and <rows-right_rbl)
|
||||
# Replic bit specifies which other bit (in the full range (0,rows) to make a replica cell.
|
||||
if (row > self.left_rbl and row < self.total_size - 1 or row == self.replica_bit):
|
||||
|
||||
if alternate_bitcell == 0:
|
||||
row_layout.append(self.replica_cell)
|
||||
self.cell_inst[row]=self.add_inst(name=name, mod=self.replica_cell)
|
||||
self.connect_inst(self.get_bitcell_pins(row, 0))
|
||||
row_layout.append(self.strap2)
|
||||
self.add_inst(name=name + "_strap", mod=self.strap2)
|
||||
self.connect_inst(self.get_strap_pins(row, 0))
|
||||
alternate_bitcell = 1
|
||||
|
||||
else:
|
||||
row_layout.append(self.replica_cell2)
|
||||
self.cell_inst[row]=self.add_inst(name=name, mod=self.replica_cell2)
|
||||
self.connect_inst(self.get_bitcell_pins(row, 0))
|
||||
row_layout.append(self.strap2)
|
||||
self.add_inst(name=name + "_strap", mod=self.strap2)
|
||||
self.connect_inst(self.get_strap_pins(row, 0))
|
||||
alternate_bitcell = 0
|
||||
|
||||
elif (row == 0):
|
||||
row_layout.append(self.colend)
|
||||
self.cell_inst[row]=self.add_inst(name=name, mod=self.colend)
|
||||
self.connect_inst(self.get_col_cap_p_pins(row, 0))
|
||||
row_layout.append(self.colend_p_cent)
|
||||
self.add_inst(name=name + "_cap", mod=self.colend_p_cent)
|
||||
self.connect_inst(self.get_col_cap_pins(row, 0))
|
||||
elif (row == self.total_size - 1):
|
||||
row_layout.append(self.colenda)
|
||||
self.cell_inst[row]=self.add_inst(name=name, mod=self.colenda)
|
||||
self.connect_inst(self.get_col_cap_p_pins(row, 0))
|
||||
row_layout.append(self.colenda_p_cent)
|
||||
self.add_inst(name=name + "_cap", mod=self.colenda_p_cent)
|
||||
self.connect_inst(self.get_col_cap_pins(row, 0))
|
||||
|
||||
self.array_layout.append(row_layout)
|
||||
|
||||
def place_instances(self, name_template="", row_offset=0):
|
||||
col_offset = self.column_offset
|
||||
yoffset = 0.0
|
||||
|
||||
for row in range(row_offset, len(self.array_layout) + row_offset):
|
||||
xoffset = 0.0
|
||||
for col in range(col_offset, len(self.array_layout[row]) + col_offset):
|
||||
self.place_inst = self.insts[(col - col_offset) + (row - row_offset) * len(self.array_layout[row - row_offset])]
|
||||
if row == row_offset or row == (len(self.array_layout) + row_offset -1):
|
||||
if row == row_offset:
|
||||
self.place_inst.place(offset=[xoffset, yoffset + self.colend.height], mirror="MX")
|
||||
else:
|
||||
self.place_inst.place(offset=[xoffset, yoffset])
|
||||
|
||||
elif col % 2 == 0:
|
||||
if row % 2 == 0:
|
||||
self.place_inst.place(offset=[xoffset, yoffset + self.place_inst.height], mirror="MX")
|
||||
else:
|
||||
self.place_inst.place(offset=[xoffset, yoffset])
|
||||
else:
|
||||
if row % 2 == 0:
|
||||
self.place_inst.place(offset=[xoffset + self.place_inst.width, yoffset + self.place_inst.height], mirror="XY")
|
||||
else:
|
||||
self.place_inst.place(offset=[xoffset + self.place_inst.width, yoffset], mirror="MY")
|
||||
|
||||
xoffset += self.place_inst.width
|
||||
if row == row_offset:
|
||||
yoffset += self.colend.height
|
||||
else:
|
||||
yoffset += self.place_inst.height
|
||||
|
||||
self.width = max([x.rx() for x in self.insts])
|
||||
self.height = max([x.uy() for x in self.insts])
|
||||
|
||||
def add_layout_pins(self):
|
||||
""" Add the layout pins """
|
||||
for port in self.all_ports:
|
||||
bl_pin = self.cell_inst[2].get_pin(self.cell.get_bl_name(port))
|
||||
self.add_layout_pin(text="bl_{0}_{1}".format(port, 0),
|
||||
layer=bl_pin.layer,
|
||||
offset=bl_pin.ll().scale(1, 0),
|
||||
width=bl_pin.width(),
|
||||
height=self.height)
|
||||
bl_pin = self.cell_inst[2].get_pin(self.cell.get_br_name(port))
|
||||
self.add_layout_pin(text="br_{0}_{1}".format(port, 0),
|
||||
layer=bl_pin.layer,
|
||||
offset=bl_pin.ll().scale(1, 0),
|
||||
width=bl_pin.width(),
|
||||
height=self.height)
|
||||
|
||||
row_range_max = self.total_size - 1
|
||||
row_range_min = 1
|
||||
|
||||
for port in self.all_ports:
|
||||
for row in range(row_range_min, row_range_max):
|
||||
wl_pin = self.cell_inst[row].get_pin(self.cell.get_wl_name(port))
|
||||
self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
|
||||
layer=wl_pin.layer,
|
||||
offset=wl_pin.ll().scale(0, 1),
|
||||
width=self.width,
|
||||
height=wl_pin.height())
|
||||
|
||||
for row in range(self.row_size + 2):
|
||||
inst = self.cell_inst[row]
|
||||
# add only 1 label per col
|
||||
for pin_name in ["vdd", "gnd"]:
|
||||
self.copy_layout_pin(inst, pin_name)
|
||||
if row == 2:
|
||||
if 'VPB' in self.cell_inst[row].mod.pins:
|
||||
pin = inst.get_pin("vpb")
|
||||
self.objs.append(geometry.rectangle(layer["nwell"],
|
||||
pin.ll(),
|
||||
pin.width(),
|
||||
pin.height()))
|
||||
self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
|
||||
|
||||
if 'VNB' in self.cell_inst[row].mod.pins:
|
||||
try:
|
||||
from tech import layer_override
|
||||
if layer_override['VNB']:
|
||||
pin = inst.get_pin("vnb")
|
||||
self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
|
||||
self.objs.append(geometry.rectangle(layer["pwellp"],
|
||||
pin.ll(),
|
||||
pin.width(),
|
||||
pin.height()))
|
||||
except:
|
||||
pin = inst.get_pin("vnb")
|
||||
self.add_label("vdd", pin.layer, pin.center())
|
||||
|
||||
def exclude_all_but_replica(self):
|
||||
"""
|
||||
Excludes all bits except the replica cell (self.replica_bit).
|
||||
"""
|
||||
for row, cell in self.cell_inst.items():
|
||||
if row != self.replica_bit:
|
||||
self.graph_inst_exclude.add(cell)
|
||||
@@ -0,0 +1,27 @@
|
||||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
import debug
|
||||
import design
|
||||
from tech import cell_properties as props
|
||||
|
||||
|
||||
class sky130_row_cap(design.design):
|
||||
|
||||
def __init__(self, version, name=""):
|
||||
|
||||
if version == "rowend":
|
||||
cell_name = "sky130_fd_bd_sram__sram_sp_rowend"
|
||||
elif version == "rowenda":
|
||||
cell_name = "sky130_fd_bd_sram__sram_sp_rowenda"
|
||||
elif version == "rowend_replica":
|
||||
cell_name = "sky130_fd_bd_sram__openram_sp_rowend_replica"
|
||||
elif version == "rowenda_replica":
|
||||
cell_name = "sky130_fd_bd_sram__openram_sp_rowenda_replica"
|
||||
else:
|
||||
debug.error("Invalid type for row_end", -1)
|
||||
super().__init__(name=name, cell_name=cell_name, prop=props.row_cap_1port_cell)
|
||||
@@ -0,0 +1,152 @@
|
||||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
from sram_factory import factory
|
||||
from sky130_bitcell_base_array import sky130_bitcell_base_array
|
||||
from globals import OPTS
|
||||
|
||||
|
||||
class sky130_row_cap_array(sky130_bitcell_base_array):
|
||||
"""
|
||||
Generate a dummy row/column for the replica array.
|
||||
"""
|
||||
def __init__(self, rows, cols, column_offset=0, mirror=0, name=""):
|
||||
# Don't call the regular col-cap_array constructor since we don't want its constructor, just
|
||||
# some of it's useful member functions
|
||||
sky130_bitcell_base_array.__init__(self, rows=rows, cols=cols, column_offset=column_offset, name=name)
|
||||
self.rows = rows
|
||||
self.cols = cols
|
||||
self.column_offset = column_offset
|
||||
self.mirror = mirror
|
||||
self.create_netlist()
|
||||
if not OPTS.netlist_only:
|
||||
self.create_layout()
|
||||
|
||||
def create_netlist(self):
|
||||
""" Create and connect the netlist """
|
||||
self.create_all_wordline_names()
|
||||
# This module has no bitlines
|
||||
# self.create_all_bitline_names()
|
||||
|
||||
self.add_modules()
|
||||
self.add_pins()
|
||||
self.create_instances()
|
||||
|
||||
def create_layout(self):
|
||||
|
||||
self.place_array("dummy_r{0}_c{1}", self.mirror)
|
||||
self.add_layout_pins()
|
||||
|
||||
self.width = max([x.rx() for x in self.insts])
|
||||
self.height = max([x.uy() for x in self.insts])
|
||||
|
||||
self.add_boundary()
|
||||
self.DRC_LVS()
|
||||
|
||||
def add_modules(self):
|
||||
""" Add the modules used in this design """
|
||||
if self.column_offset == 0:
|
||||
self.top_corner = factory.create(module_type="corner", location="ul")
|
||||
self.add_mod(self.top_corner)
|
||||
self.bottom_corner =factory.create(module_type="corner", location="ll")
|
||||
self.add_mod(self.bottom_corner)
|
||||
self.rowend1 = factory.create(module_type="row_cap", version="rowend_replica")
|
||||
self.add_mod(self.rowend1)
|
||||
self.rowend2 = factory.create(module_type="row_cap", version="rowenda_replica")
|
||||
self.add_mod(self.rowend2)
|
||||
|
||||
else:
|
||||
self.top_corner = factory.create(module_type="corner", location="ur")
|
||||
self.add_mod(self.top_corner)
|
||||
self.bottom_corner = factory.create(module_type="corner", location="lr")
|
||||
self.add_mod(self.bottom_corner)
|
||||
|
||||
self.rowend1 = factory.create(module_type="row_cap", version="rowend")
|
||||
self.add_mod(self.rowend1)
|
||||
self.rowend2 = factory.create(module_type="row_cap", version="rowenda")
|
||||
self.add_mod(self.rowend2)
|
||||
|
||||
self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
|
||||
|
||||
def create_instances(self):
|
||||
""" Create the module instances used in this design """
|
||||
self.cell_inst = {}
|
||||
self.array_layout = []
|
||||
alternate_bitcell = (self.rows + 1) % 2
|
||||
for row in range(self.rows + 2):
|
||||
row_layout = []
|
||||
name="rca_{0}".format(row)
|
||||
# Top/bottom cell are always dummy cells.
|
||||
# Regular array cells are replica cells (>left_rbl and <rows-right_rbl)
|
||||
# Replic bit specifies which other bit (in the full range (0,rows) to make a replica cell.
|
||||
|
||||
if (row < self.rows + 1 and row > 0):
|
||||
|
||||
if alternate_bitcell == 0:
|
||||
row_layout.append(self.rowend1)
|
||||
self.cell_inst[row]=self.add_inst(name=name, mod=self.rowend1)
|
||||
self.connect_inst(["wl_0_{}".format(row - 1), "vdd"])
|
||||
alternate_bitcell = 1
|
||||
|
||||
else:
|
||||
row_layout.append(self.rowend2)
|
||||
self.cell_inst[row] = self.add_inst(name=name, mod=self.rowend2)
|
||||
self.connect_inst(["wl_0_{}".format(row - 1), "vdd"])
|
||||
alternate_bitcell = 0
|
||||
|
||||
elif (row == 0):
|
||||
row_layout.append(self.bottom_corner)
|
||||
self.cell_inst[row]=self.add_inst(name=name, mod=self.bottom_corner)
|
||||
self.connect_inst(self.get_corner_pins())
|
||||
|
||||
elif (row == self.rows + 1):
|
||||
row_layout.append(self.top_corner)
|
||||
self.cell_inst[row]=self.add_inst(name=name, mod=self.top_corner)
|
||||
self.connect_inst(self.get_corner_pins())
|
||||
|
||||
self.array_layout.append(row_layout)
|
||||
|
||||
def place_array(self, name_template, row_offset=0):
|
||||
xoffset = 0.0
|
||||
yoffset = 0.0
|
||||
for row in range(len(self.insts)):
|
||||
inst = self.insts[row]
|
||||
if row == 0:
|
||||
inst.place(offset=[xoffset, yoffset + inst.height], mirror="MX")
|
||||
elif row == len(self.insts)-1:
|
||||
inst.place(offset=[xoffset, yoffset])
|
||||
else:
|
||||
if row % 2 ==0:
|
||||
inst.place(offset=[xoffset, yoffset + inst.height], mirror="MX")
|
||||
else:
|
||||
inst.place(offset=[xoffset, yoffset])
|
||||
yoffset += inst.height
|
||||
|
||||
def add_pins(self):
|
||||
for row in range(self.rows + 2):
|
||||
for port in self.all_ports:
|
||||
self.add_pin("wl_{}_{}".format(port, row), "OUTPUT")
|
||||
self.add_pin("vdd", "POWER")
|
||||
self.add_pin("gnd", "GROUND")
|
||||
|
||||
def add_layout_pins(self):
|
||||
""" Add the layout pins """
|
||||
for row in range(0, self.rows + 1):
|
||||
if row > 0 and row < self.rows + 1:
|
||||
wl_pin = self.cell_inst[row].get_pin("wl")
|
||||
self.add_layout_pin(text="wl_0_{0}".format(row -1),
|
||||
layer=wl_pin.layer,
|
||||
offset=wl_pin.ll().scale(0, 1),
|
||||
width=self.width,
|
||||
height=wl_pin.height())
|
||||
|
||||
# Add vdd/gnd via stacks
|
||||
for row in range(1, self.rows):
|
||||
inst = self.cell_inst[row]
|
||||
for pin_name in ["vdd", "gnd"]:
|
||||
for pin in inst.get_pins(pin_name):
|
||||
self.copy_layout_pin(inst, pin_name)
|
||||
Reference in New Issue
Block a user