route bias pisn

compiler/base/hierarchy_layout.py

@@ -1203,22 +1203,24 @@ class layout():
                              height=ymax - ymin)
         return rect
 
-    def copy_power_pins(self, inst, name, add_vias=True):
+    def copy_power_pins(self, inst, name, add_vias=True, new_name=""):
         """
         This will copy a power pin if it is on the lowest power_grid layer.
         If it is on M1, it will add a power via too.
         """
         pins = inst.get_pins(name)
         for pin in pins:
+            if new_name == "":
+                new_name = pin.name
             if pin.layer == self.pwr_grid_layer:
-                self.add_layout_pin(name,
+                self.add_layout_pin(new_name,
                                     pin.layer,
                                     pin.ll(),
                                     pin.width(),
                                     pin.height())
 
             elif add_vias:
-                self.copy_power_pin(pin)
+                self.copy_power_pin(pin, new_name=new_name)
 
     def add_io_pin(self, instance, pin_name, new_name, start_layer=None):
         """
@@ -1264,13 +1266,15 @@ class layout():
                                             width=width,
                                             height=height)
 
-    def copy_power_pin(self, pin, loc=None, directions=None):
+    def copy_power_pin(self, pin, loc=None, directions=None, new_name=""):
         """
         Add a single power pin from the lowest power_grid layer down to M1 (or li) at
         the given center location. The starting layer is specified to determine
         which vias are needed.
         """
 
+        if new_name == "":
+                new_name = pin.name
         if not loc:
             loc = pin.center()
             
@@ -1284,7 +1288,7 @@ class layout():
             height = None
             
         if pin.layer == self.pwr_grid_layer:
-            self.add_layout_pin_rect_center(text=pin.name,
+            self.add_layout_pin_rect_center(text=new_name,
                                             layer=self.pwr_grid_layer,
                                             offset=loc,
                                             width=width,
@@ -1299,7 +1303,7 @@ class layout():
                 width = via.width
             if not height:
                 height = via.height
-            self.add_layout_pin_rect_center(text=pin.name,
+            self.add_layout_pin_rect_center(text=new_name,
                                             layer=self.pwr_grid_layer,
                                             offset=loc,
                                             width=width,

compiler/modules/bank.py

@@ -439,6 +439,9 @@ class bank(design.design):
 
         temp.append("vdd")
         temp.append("gnd")
+        if 'vpb' in self.bitcell_array_inst.mod.pins and 'vnb' in self.bitcell_array_inst.mod.pins:
+            temp.append('vpb')
+            temp.append('vnb')
         self.connect_inst(temp)
 
     def place_bitcell_array(self, offset):
@@ -622,6 +625,10 @@ class bank(design.design):
             self.copy_power_pins(inst, "vdd", add_vias=False)
             self.copy_power_pins(inst, "gnd", add_vias=False)
 
+        #if 'vpb' in self.bitcell_array_inst.mod.pins and 'vnb' in self.bitcell_array_inst.mod.pins:
+        #    for pin_name, supply_name in zip(['vpb','vnb'],['vdd','gnd']):
+        #        self.copy_power_pins(self.bitcell_array_inst, pin_name, new_name=supply_name)
+
         # If we use the pinvbuf as the decoder, we need to add power pins.
         # Other decoders already have them.
         if self.col_addr_size == 1:
@@ -1070,7 +1077,6 @@ class bank(design.design):
                                       to_layer="m2",
                                       offset=control_pos)
 
-
     def graph_exclude_precharge(self):
         """
         Precharge adds a loop between bitlines, can be excluded to reduce complexity

compiler/router/pin_group.py

@@ -149,6 +149,7 @@ class pin_group:
             pin_list.append(enclosure)
 
         if len(pin_list) == 0:
+            breakpoint()
             debug.error("Did not find any enclosures for {}".format(self.name))
             self.router.write_debug_gds("pin_enclosure_error.gds")
 

compiler/verify/magic.py

@@ -86,7 +86,7 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa
     f.write("{} -dnull -noconsole << EOF\n".format(OPTS.drc_exe[1]))
     # Do not run DRC for extraction/conversion
     f.write("drc off\n")
-    f.write("gds polygon subcell true\n")
+    # f.write("gds polygon subcell true\n")
     f.write("gds warning default\n")
     # These two options are temporarily disabled until Tim fixes a bug in magic related
     # to flattening channel routes and vias (hierarchy with no devices in it). Otherwise,