route bias pisn

compiler/modules/bank.py

@@ -439,6 +439,9 @@ class bank(design.design):
 
         temp.append("vdd")
         temp.append("gnd")
+        if 'vpb' in self.bitcell_array_inst.mod.pins and 'vnb' in self.bitcell_array_inst.mod.pins:
+            temp.append('vpb')
+            temp.append('vnb')
         self.connect_inst(temp)
 
     def place_bitcell_array(self, offset):
@@ -622,6 +625,10 @@ class bank(design.design):
             self.copy_power_pins(inst, "vdd", add_vias=False)
             self.copy_power_pins(inst, "gnd", add_vias=False)
 
+        #if 'vpb' in self.bitcell_array_inst.mod.pins and 'vnb' in self.bitcell_array_inst.mod.pins:
+        #    for pin_name, supply_name in zip(['vpb','vnb'],['vdd','gnd']):
+        #        self.copy_power_pins(self.bitcell_array_inst, pin_name, new_name=supply_name)
+
         # If we use the pinvbuf as the decoder, we need to add power pins.
         # Other decoders already have them.
         if self.col_addr_size == 1:
@@ -1070,7 +1077,6 @@ class bank(design.design):
                                       to_layer="m2",
                                       offset=control_pos)
 
-
     def graph_exclude_precharge(self):
         """
         Precharge adds a loop between bitlines, can be excluded to reduce complexity