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Route precharge vdd to M3

This commit is contained in:
Matt Guthaus 2018-04-04 13:34:56 -07:00
parent a35fc1f339
commit f9916f9f43
1 changed files with 18 additions and 6 deletions
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24
compiler/modules/precharge.py
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@ -57,13 +57,25 @@ class precharge(pgate.pgate):
"""Adds a vdd rail at the top of the cell""" """Adds a vdd rail at the top of the cell"""
# adds the rail across the width of the cell # adds the rail across the width of the cell
vdd_position = vector(0, self.height - self.m1_width) vdd_position = vector(0, self.height - self.m1_width)
self.add_layout_pin(text="vdd", self.add_rect(layer="metal1",
layer="metal1", offset=vdd_position,
offset=vdd_position, width=self.width,
width=self.width, height=self.m1_width)
height=self.m1_width)
self.connect_pin_to_rail(self.upper_pmos2_inst,"S","vdd") pmos_pin = self.upper_pmos2_inst.get_pin("S")
# center of vdd rail
vdd_pos = vector(pmos_pin.cx(), vdd_position.y + 0.5*self.m1_width)
self.add_path("metal1", [pmos_pin.uc(), vdd_pos])
# Always drop to M1
self.add_via_center(layers=("metal1", "via1", "metal2"),
offset=vdd_pos)
self.add_via_center(layers=("metal2", "via2", "metal3"),
offset=vdd_pos)
self.add_layout_pin_rect_center(text="vdd",
layer="metal3",
offset=vdd_pos)
def add_ptx(self): def add_ptx(self):
"""Adds both the upper_pmos and lower_pmos to the module""" """Adds both the upper_pmos and lower_pmos to the module"""