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Single bank passing.

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Parameterized gate column mux of dff height.
End-cap only supply option instead of no vdd in bitcell.
This commit is contained in:
mrg
2020-06-25 14:03:59 -07:00
parent ee0a003298
commit f84ee04fa9
6 changed files with 61 additions and 51 deletions
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compiler/modules/hierarchical_decoder.py
+2 -4
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@@ -78,12 +78,10 @@ class hierarchical_decoder(design.design):
def add_decoders(self):
""" Create the decoders based on the number of pre-decodes """
self.pre2_4 = factory.create(module_type="hierarchical_predecode2x4",
height=self.cell_height)
self.pre2_4 = factory.create(module_type="hierarchical_predecode2x4")
self.add_mod(self.pre2_4)
self.pre3_8 = factory.create(module_type="hierarchical_predecode3x8",
height=self.cell_height)
self.pre3_8 = factory.create(module_type="hierarchical_predecode3x8")
self.add_mod(self.pre3_8)
def determine_predecodes(self, num_inputs):