luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 01:48:33 +02:00
Code Issues Packages Projects Releases Wiki Activity

Single bank passing.

Browse Source 
Parameterized gate column mux of dff height.
End-cap only supply option instead of no vdd in bitcell.
This commit is contained in:
mrg
2020-06-25 14:03:59 -07:00
parent ee0a003298
commit f84ee04fa9
6 changed files with 61 additions and 51 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/bitcell_base_array.py
+8 -8
View File
@@ -110,17 +110,17 @@ class bitcell_base_array(design.design):
# For specific technologies, there is no vdd via within the bitcell. Instead vdd is connect via end caps.
try:
bitcell_no_vdd_pin = cell_properties.bitcell.no_vdd_via
end_caps_enabled = cell_properties.bitcell.end_caps
except AttributeError:
bitcell_no_vdd_pin = False
end_caps_enabled = False
# Add vdd/gnd via stacks
for row in range(self.row_size):
for col in range(self.column_size):
inst = self.cell_inst[row,col]
for pin_name in ["vdd", "gnd"]:
for pin in inst.get_pins(pin_name):
if not (pin_name == "vdd" and bitcell_no_vdd_pin):
if not end_caps_enabled:
for row in range(self.row_size):
for col in range(self.column_size):
inst = self.cell_inst[row, col]
for pin_name in ["vdd", "gnd"]:
for pin in inst.get_pins(pin_name):
self.add_power_pin(name=pin_name,
loc=pin.center(),
directions=bitcell_power_pin_directions,