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Fix wrong bit size in fake_sram.

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mrg 2023-07-20 10:11:49 -07:00
parent f246e5a521
commit f800b50813
1 changed files with 1 additions and 1 deletions
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2
compiler/characterizer/fake_sram.py
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@ -89,7 +89,7 @@ class fake_sram(sram_config):
self.pins.extend(['dout{0}[{1}]'.format(port, bit)
for bit in range(self.word_size + self.num_spare_cols)])
self.pins.extend(['addr{0}[{1}]'.format(port, bit)
for bit in range(self.word_size)])
for bit in range(self.addr_size)])
self.pins.extend(['csb{}'.format(port)])