mirror of https://github.com/VLSIDA/OpenRAM.git
Fix wrong bit size in fake_sram.
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@ -89,7 +89,7 @@ class fake_sram(sram_config):
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self.pins.extend(['dout{0}[{1}]'.format(port, bit)
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self.pins.extend(['dout{0}[{1}]'.format(port, bit)
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for bit in range(self.word_size + self.num_spare_cols)])
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for bit in range(self.word_size + self.num_spare_cols)])
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self.pins.extend(['addr{0}[{1}]'.format(port, bit)
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self.pins.extend(['addr{0}[{1}]'.format(port, bit)
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for bit in range(self.word_size)])
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for bit in range(self.addr_size)])
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self.pins.extend(['csb{}'.format(port)])
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self.pins.extend(['csb{}'.format(port)])
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