luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Format fixes

This commit is contained in:
Bugra Onal 2023-02-22 12:38:47 -08:00
parent 6eb0ecd82b
commit f7f61fee27
1 changed files with 3 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
compiler/characterizer/delay.py
View File

@ -1261,19 +1261,18 @@ class delay(simulation):
def guess_spice_names(self): def guess_spice_names(self):
"""This is run in place of set_internal_spice_names function from """This is run in place of set_internal_spice_names function from
simulation.py when running stand-alone characterizer.""" simulation.py when running stand-alone characterizer."""
# TODO: Find a better method
with open(self.sp_file, "r") as file: with open(self.sp_file, "r") as file:
bl_prefix = None bl_prefix = None
br_prefix = None br_prefix = None
replica_bitcell_array_name = None replica_bitcell_array_name = None
for line in file: for line in file:
if re.search("bl_\d_\d", line): if re.search(r"bl_\d_\d", line):
bl_prefix = "bl_" bl_prefix = "bl_"
br_prefix = "br_" br_prefix = "br_"
if re.search("bl\d_\d", line): if re.search(r"bl\d_\d", line):
bl_prefix = "bl" bl_prefix = "bl"
br_prefix = "br" br_prefix = "br"
if re.search("Xreplica_bitcell_array", line): if re.search(r"Xreplica_bitcell_array", line):
replica_bitcell_array_name = "replica_bitcell_array" replica_bitcell_array_name = "replica_bitcell_array"
if bl_prefix and replica_bitcell_array_name: if bl_prefix and replica_bitcell_array_name:
break break
@ -1285,10 +1284,6 @@ class delay(simulation):
replica_bitcell_array_name = "bitcell_array" replica_bitcell_array_name = "bitcell_array"
self.cell_format = "X{{0}}{{3}}xbank0{{3}}x{0}{{3}}xbitcell_array{{3}}xbit_r{{1}}_c{{2}}".format(replica_bitcell_array_name) self.cell_format = "X{{0}}{{3}}xbank0{{3}}x{0}{{3}}xbitcell_array{{3}}xbit_r{{1}}_c{{2}}".format(replica_bitcell_array_name)
def analysis_init(self, probe_address, probe_data): def analysis_init(self, probe_address, probe_data):
"""Sets values which are dependent on the data address/bit being tested.""" """Sets values which are dependent on the data address/bit being tested."""