Remove tri_en signals from bank control logic.

compiler/modules/bank.py

@@ -22,9 +22,9 @@ class bank(design.design):
 
     def __init__(self, word_size, num_words, words_per_row, num_banks=1, name=""):
 
-        mod_list = ["tri_gate", "bitcell", "decoder", "ms_flop_array", "wordline_driver",
+        mod_list = ["bitcell", "decoder", "ms_flop_array", "wordline_driver",
                     "bitcell_array",   "sense_amp_array",    "precharge_array",
-                    "column_mux_array", "write_driver_array", "tri_gate_array",
+                    "column_mux_array", "write_driver_array", 
                     "dff", "bank_select"]
         from importlib import reload
         for mod_name in mod_list:
@@ -84,8 +84,7 @@ class bank(design.design):
         # the signals gated_*.
         if self.num_banks > 1:
             self.add_pin("bank_sel","INPUT")
-        for pin in ["s_en","w_en","tri_en_bar","tri_en",
+        for pin in ["s_en","w_en","clk_buf_bar","clk_buf"]:
-                    "clk_buf_bar","clk_buf"]:
             self.add_pin(pin,"INPUT")
         self.add_pin("vdd","POWER")
         self.add_pin("gnd","GROUND")
@@ -96,8 +95,6 @@ class bank(design.design):
         self.route_precharge_to_bitcell_array()
         self.route_col_mux_to_bitcell_array()
         self.route_sense_amp_to_col_mux_or_bitcell_array()
-        #self.route_sense_amp_to_trigate()
-        #self.route_tri_gate_out()
         self.route_sense_amp_out()
         self.route_wordline_driver()
         self.route_write_driver()        
@@ -121,8 +118,6 @@ class bank(design.design):
         self.add_column_mux_array()
         self.add_sense_amp_array()
         self.add_write_driver_array()
-        # Not needed for single bank
-        #self.add_tri_gate_array()
 
         # To the left of the bitcell array
         self.add_row_decoder()
@@ -150,9 +145,9 @@ class bank(design.design):
         self.supply_rail_pitch = self.supply_rail_width + 4*self.m2_space
         
         # Number of control lines in the bus
-        self.num_control_lines = 6
+        self.num_control_lines = 4
         # The order of the control signals on the control bus:
-        self.input_control_signals = ["clk_buf", "tri_en_bar", "tri_en", "clk_buf_bar", "w_en", "s_en"]
+        self.input_control_signals = ["clk_buf", "clk_buf_bar", "w_en", "s_en"]
         # These will be outputs of the gaters if this is multibank, if not, normal signals.
         if self.num_banks > 1:
             self.control_signals = ["gated_"+str for str in self.input_control_signals]
@@ -176,7 +171,6 @@ class bank(design.design):
 
     def create_modules(self):
         """ Create all the modules using the class loader """
-        self.tri = self.mod_tri_gate()
         self.bitcell = self.mod_bitcell()
         
         self.bitcell_array = self.mod_bitcell_array(cols=self.num_cols,
@@ -203,10 +197,6 @@ class bank(design.design):
         self.row_decoder = self.mod_decoder(rows=self.num_rows)
         self.add_mod(self.row_decoder)
         
-        self.tri_gate_array = self.mod_tri_gate_array(columns=self.num_cols, 
-                                                      word_size=self.word_size)
-        self.add_mod(self.tri_gate_array)
-
         self.wordline_driver = self.mod_wordline_driver(rows=self.num_rows)
         self.add_mod(self.wordline_driver)
 
@@ -316,22 +306,6 @@ class bank(design.design):
         temp.extend([self.prefix+"w_en", "vdd", "gnd"])
         self.connect_inst(temp)
 
-    def add_tri_gate_array(self):
-        """ data tri gate to drive the data bus """
-        y_offset = self.sense_amp_array.height+self.column_mux_height \
-            + self.m2_gap + self.tri_gate_array.height
-        self.tri_gate_array_inst=self.add_inst(name="tri_gate_array", 
-                                               mod=self.tri_gate_array, 
-                                               offset=vector(0,y_offset).scale(-1,-1))
-                  
-        temp = []
-        for i in range(self.word_size):
-            temp.append("sa_out[{0}]".format(i))
-        for i in range(self.word_size):
-            temp.append("dout[{0}]".format(i))
-        temp.extend([self.prefix+"tri_en", self.prefix+"tri_en_bar", "vdd", "gnd"])
-        self.connect_inst(temp)
-
     def add_row_decoder(self):
         """  Add the hierarchical row decoder  """
 
@@ -447,7 +421,6 @@ class bank(design.design):
                          self.precharge_array_inst,
                          self.sense_amp_array_inst,
                          self.write_driver_array_inst,
-#                         self.tri_gate_array_inst,
                          self.row_decoder_inst,
                          self.wordline_driver_inst]
         # Add these if we use the part...
@@ -493,10 +466,7 @@ class bank(design.design):
         control bus, power ring, etc. """
 
         #The minimum point is either the bottom of the address flops,
-        #the column decoder (if there is one) or the tristate output
+        #the column decoder (if there is one).
-        #driver.
-        # Leave room for the output below the tri gate.
-        #tri_gate_min_y_offset = self.tri_gate_array_inst.by() - 3*self.m2_pitch
         write_driver_min_y_offset = self.write_driver_array_inst.by() - 3*self.m2_pitch        
         row_decoder_min_y_offset = self.row_decoder_inst.by()
         if self.col_addr_size > 0:
@@ -506,10 +476,10 @@ class bank(design.design):
         
         if self.num_banks>1:
             # The control gating logic is below the decoder
-            # Min of the control gating logic and tri gate.
+            # Min of the control gating logic and write driver.
             self.min_y_offset = min(col_decoder_min_y_offset - self.bank_select.height, write_driver_min_y_offset)
         else:
-            # Just the min of the decoder logic logic and tri gate.            
+            # Just the min of the decoder logic logic and write driver.
             self.min_y_offset = min(col_decoder_min_y_offset, write_driver_min_y_offset)
 
         # The max point is always the top of the precharge bitlines
@@ -603,20 +573,6 @@ class bank(design.design):
             self.add_path("metal2",[sense_amp_br, vector(sense_amp_br.x,yoffset),
                                     vector(connect_br.x,yoffset), connect_br])
             
-    def route_sense_amp_to_trigate(self):
-        """ Routing of sense amp output to tri_gate input """
-
-        for i in range(self.word_size):
-            # Connection of data_out of sense amp to data_in 
-            tri_gate_in = self.tri_gate_array_inst.get_pin("in[{}]".format(i)).lc()
-            sa_data_out = self.sense_amp_array_inst.get_pin("data[{}]".format(i)).bc()
-
-            self.add_via_center(layers=("metal2", "via2", "metal3"),
-                                offset=tri_gate_in)
-            self.add_via_center(layers=("metal2", "via2", "metal3"),
-                                offset=sa_data_out)
-            self.add_path("metal3",[sa_data_out,tri_gate_in])
-
     def route_sense_amp_out(self):
         """ Add pins for the sense amp output """
         for i in range(self.word_size):
@@ -627,17 +583,6 @@ class bank(design.design):
                                             height=data_pin.height(),
                                             width=data_pin.width()),
         
-    def route_tri_gate_out(self):
-        """ Metal 3 routing of tri_gate output data """
-        for i in range(self.word_size):
-            data_pin = self.tri_gate_array_inst.get_pin("out[{}]".format(i))
-            self.add_layout_pin_rect_center(text="dout[{}]".format(i),
-                                            layer=data_pin.layer, 
-                                            offset=data_pin.center(),
-                                            height=data_pin.height(),
-                                            width=data_pin.width()),
-
-
     def route_row_decoder(self):
         """ Routes the row decoder inputs and supplies """
 
@@ -782,8 +727,6 @@ class bank(design.design):
         # Connection from the central bus to the main control block crosses
         # pre-decoder and this connection is in metal3
         connection = []
-        #connection.append((self.prefix+"tri_en_bar", self.tri_gate_array_inst.get_pin("en_bar").lc()))
-        #connection.append((self.prefix+"tri_en", self.tri_gate_array_inst.get_pin("en").lc()))
         connection.append((self.prefix+"clk_buf_bar", self.precharge_array_inst.get_pin("en").lc()))
         connection.append((self.prefix+"w_en", self.write_driver_array_inst.get_pin("en").lc()))
         connection.append((self.prefix+"s_en", self.sense_amp_array_inst.get_pin("en").lc()))
@@ -866,8 +809,6 @@ class bank(design.design):
                                                                     self.bitcell_array.output_load())
         # output load of bitcell_array is set to be only small part of bl for sense amp.
 
-        data_t_DATA_delay = self.tri_gate_array.analytical_delay(bl_t_data_out_delay.slew, load)
+        result = decoder_delay + word_driver_delay + bitcell_array_delay + bl_t_data_out_delay 
-
-        result = decoder_delay + word_driver_delay + bitcell_array_delay + bl_t_data_out_delay + data_t_DATA_delay
         return result
         

compiler/modules/bank_select.py

@@ -19,9 +19,9 @@ class bank_select(design.design):
         design.design.__init__(self, name)
 
         # Number of control lines in the bus
-        self.num_control_lines = 6
+        self.num_control_lines = 4
         # The order of the control signals on the control bus:
-        self.input_control_signals = ["clk_buf", "tri_en_bar", "tri_en", "clk_buf_bar", "w_en", "s_en"]
+        self.input_control_signals = ["clk_buf", "clk_buf_bar", "w_en", "s_en"]
         # These will be outputs of the gaters if this is multibank
         self.control_signals = ["gated_"+str for str in self.input_control_signals]
 
@@ -96,7 +96,7 @@ class bank_select(design.design):
             
             # These require OR (nor2+inv) gates since they are active low.
             # (writes occur on clk low)
-            if input_name in ("clk_buf", "tri_en_bar"):
+            if input_name in ("clk_buf"):
                 
                 self.logic_inst.append(self.add_inst(name=name_nor, 
                                          mod=self.nor2, 
@@ -173,7 +173,7 @@ class bank_select(design.design):
             
             input_name = self.input_control_signals[i]
             gated_name = self.control_signals[i]            
-            if input_name in ("clk_buf", "tri_en_bar"):
+            if input_name in ("clk_buf"):
                 xoffset_bank_signal = xoffset_bank_sel_bar
             else:
                 xoffset_bank_signal = xoffset_bank_sel

compiler/modules/control_logic.py

@@ -101,8 +101,6 @@ class control_logic(design.design):
         self.internal_bus_width = (len(self.internal_bus_list)+1)*self.m2_pitch 
         # Ooutputs to the bank
         self.output_list = ["s_en", "w_en", "clk_buf_bar", "clk_buf"]
-        # # with tri/tri_en
-        # self.output_list = ["s_en", "w_en", "tri_en", "tri_en_bar", "clk_buf_bar", "clk_buf"]        
         self.supply_list = ["vdd", "gnd"]
 
     
@@ -237,71 +235,6 @@ class control_logic(design.design):
 
         self.row_end_inst.append(self.s_en_inst)
         
-    def add_trien_row(self, row):
-        x_off = self.ctrl_dff_array.width + self.internal_bus_width
-        (y_off,mirror)=self.get_offset(row)
-        
-        
-        x_off += self.nand2.width
- 
-        # BUFFER INVERTERS FOR TRI_EN
-        tri_en_offset = vector(x_off, y_off)
-        self.tri_en_inst=self.add_inst(name="inv_tri_en1",
-                                       mod=self.inv2,
-                                       offset=tri_en_offset,
-                                       mirror=mirror)
-        self.connect_inst(["pre_tri_en_bar", "pre_tri_en1",  "vdd", "gnd"])
-        x_off += self.inv2.width
-        
-        tri_en_buf1_offset = vector(x_off, y_off)
-        self.tri_en_buf1_inst=self.add_inst(name="tri_en_buf1",
-                                            mod=self.inv2,
-                                            offset=tri_en_buf1_offset,
-                                            mirror=mirror)
-        self.connect_inst(["pre_tri_en1", "pre_tri_en_bar1",  "vdd", "gnd"])
-        x_off += self.inv2.width
-
-        tri_en_buf2_offset = vector(x_off,  y_off)
-        self.tri_en_buf2_inst=self.add_inst(name="tri_en_buf2",
-                                            mod=self.inv8,
-                                            offset=tri_en_buf2_offset,
-                                            mirror=mirror)
-        self.connect_inst(["pre_tri_en_bar1", "tri_en",  "vdd", "gnd"])
-        
-        self.row_end_inst.append(self.tri_en_inst)
-
-    def add_trien_bar_row(self, row):
-        x_off = self.ctrl_dff_array.width + self.internal_bus_width
-        (y_off,mirror)=self.get_offset(row)
-
- 
-        # input: OE, clk_buf_bar output: tri_en_bar
-        tri_en_bar_offset = vector(x_off,y_off)
-        self.tri_en_bar_inst=self.add_inst(name="nand2_tri_en",
-                                           mod=self.nand2,
-                                           offset=tri_en_bar_offset,
-                                           mirror=mirror)
-        self.connect_inst(["clk_buf_bar", "oe",  "pre_tri_en_bar", "vdd", "gnd"])
-        x_off += self.nand2.width 
-
-        # BUFFER INVERTERS FOR TRI_EN
-        tri_en_bar_buf1_offset = vector(x_off, y_off)
-        self.tri_en_bar_buf1_inst=self.add_inst(name="tri_en_bar_buf1",
-                                                mod=self.inv2,
-                                                offset=tri_en_bar_buf1_offset,
-                                                mirror=mirror)
-        self.connect_inst(["pre_tri_en_bar", "pre_tri_en2",  "vdd", "gnd"])
-        x_off += self.inv2.width
-
-        tri_en_bar_buf2_offset = vector(x_off,  y_off)
-        self.tri_en_bar_buf2_inst=self.add_inst(name="tri_en_bar_buf2",
-                                                mod=self.inv8,
-                                                offset=tri_en_bar_buf2_offset,
-                                                mirror=mirror)
-        self.connect_inst(["pre_tri_en2", "tri_en_bar",  "vdd", "gnd"])
-        x_off += self.inv8.width
-        
-        self.row_end_inst.append(self.tri_en_bar_buf2_inst)
         
     def route_dffs(self):
         """ Route the input inverters """
@@ -474,44 +407,6 @@ class control_logic(design.design):
 
         self.connect_output(self.w_en_inst, "Z", "w_en")
         
-    def route_trien(self):
-
-        # Connect the NAND2 output to the buffer
-        tri_en_bar_pos = self.tri_en_bar_inst.get_pin("Z").center()
-        inv_in_pos = self.tri_en_inst.get_pin("A").center()
-        mid1 = vector(tri_en_bar_pos.x,inv_in_pos.y)
-        self.add_wire(("metal1","via1","metal2"),[tri_en_bar_pos,mid1,inv_in_pos])
-        
-        # Connect the INV output to the buffer
-        tri_en_pos = self.tri_en_inst.get_pin("Z").center()
-        inv_in_pos = self.tri_en_buf1_inst.get_pin("A").center()
-        mid_xoffset = 0.5*(tri_en_pos.x + inv_in_pos.x)
-        mid1 = vector(mid_xoffset,tri_en_pos.y)
-        mid2 = vector(mid_xoffset,inv_in_pos.y)        
-        self.add_path("metal1",[tri_en_pos,mid1,mid2,inv_in_pos])
-        
-        self.add_path("metal1",[self.tri_en_buf1_ist.get_pin("Z").center(), self.tri_en_buf2_inst.get_pin("A").center()])                      
-        
-        self.connect_output(self.tri_en_buf2_inst, "Z", "tri_en")
-        
-    def route_trien_bar(self):
-        
-        trien_map = zip(["A", "B"], ["clk_buf_bar", "oe"])
-        self.connect_vertical_bus(trien_map, self.tri_en_bar_inst, self.rail_offsets)  
-
-        # Connect the NAND2 output to the buffer
-        tri_en_bar_pos = self.tri_en_bar_inst.get_pin("Z").center()
-        inv_in_pos = self.tri_en_bar_buf1_inst.get_pin("A").center()
-        mid_xoffset = 0.5*(tri_en_bar_pos.x + inv_in_pos.x)
-        mid1 = vector(mid_xoffset,tri_en_bar_pos.y)
-        mid2 = vector(mid_xoffset,inv_in_pos.y)        
-        self.add_path("metal1",[tri_en_bar_pos,mid1,mid2,inv_in_pos])
-
-        self.add_path("metal1",[self.tri_en_bar_buf1_inst.get_pin("Z").center(), self.tri_en_bar_buf2_inst.get_pin("A").center()])                      
-        
-        self.connect_output(self.tri_en_bar_buf2_inst, "Z", "tri_en_bar")
-        
-
     def route_sen(self):
         rbl_out_pos = self.rbl_inst.get_pin("out").bc()
         in_pos = self.pre_s_en_bar_inst.get_pin("A").lc()

compiler/sram_base.py

@@ -150,7 +150,7 @@ class sram_base(design):
         """ Add the horizontal and vertical busses """
         # Vertical bus
         # The order of the control signals on the control bus:
-        self.control_bus_names = ["clk_buf", "tri_en_bar", "tri_en", "clk_buf_bar", "w_en", "s_en"]
+        self.control_bus_names = ["clk_buf", "clk_buf_bar", "w_en", "s_en"]
         self.vert_control_bus_positions = self.create_vertical_bus(layer="metal2",
                                                                    pitch=self.m2_pitch,
                                                                    offset=self.vertical_bus_offset,
@@ -328,8 +328,7 @@ class sram_base(design):
             temp.append("A[{0}]".format(i))
         if(self.num_banks > 1):
             temp.append("bank_sel[{0}]".format(bank_num))
-        temp.extend(["s_en", "w_en", "tri_en_bar", "tri_en",
+        temp.extend(["s_en", "w_en", "clk_buf_bar","clk_buf" , "vdd", "gnd"])
-                     "clk_buf_bar","clk_buf" , "vdd", "gnd"])
         self.connect_inst(temp)
 
         return bank_inst

compiler/tests/21_hspice_delay_test.py

@@ -62,16 +62,16 @@ class timing_sram_test(openram_test):
                             'write0_power': [0.0494321],
                             'write1_power': [0.0457268]}
         elif OPTS.tech_name == "scn3me_subm":
-            golden_data = {'delay_hl': [6.0052],
+            golden_data = {'delay_hl': [3.6602],
-                            'delay_lh': [2.2886],
+                            'delay_lh': [2.2651],
-                            'leakage_power': 0.025629199999999998,
+                            'leakage_power': 0.026040400000000002,
-                            'min_period': 9.375,
+                            'min_period': 4.688,
-                            'read0_power': [8.8721],
+                            'read0_power': [15.8985],
-                            'read1_power': [8.3179],
+                            'read1_power': [14.9719],
-                            'slew_hl': [1.0746],
+                            'slew_hl': [1.1001],
-                            'slew_lh': [0.413426],
+                            'slew_lh': [0.4111598],
-                            'write0_power': [8.6601],
+                            'write0_power': [19.4539],
-                            'write1_power': [8.0397]}
+                            'write1_power': [16.8561]}
         else:
             self.assertTrue(False) # other techs fail
         # Check if no too many or too few results