column control and address precharge

compiler/tests/05_rom_array_test.py

@@ -25,7 +25,7 @@ class rom_array_test(openram_test):
         debug.info(2, "Testing 4x4 array for rom cell")
 
 
-        data = [[1, 0, 0, 0, 0, 1, 0, 0, 1], [0, 1, 1, 1, 0, 1, 0, 0, 1], [1, 0, 1, 1, 0, 1, 0, 0, 1], [1, 1, 0, 1, 1, 0, 0, 0, 1], [1, 0, 0, 0, 1, 0, 0, 0, 1], [0, 1, 1, 1, 1, 0, 0, 0, 1], [1, 0, 1, 1, 1, 0, 0, 0, 1], [1, 1, 0, 0, 1, 1, 0, 0, 1]]
+        data = [[1, 0, 0, 1, 0, 0, 1, 1, 0], [0, 1, 0, 0, 1, 0, 1, 0, 0], [0, 0, 1, 0, 0, 0, 1, 0, 0], [0, 0, 0, 0, 1, 0, 0, 0, 1], [0, 1, 0, 0, 1, 1, 0, 0, 1], [0, 0, 0, 0, 0, 0, 0, 1, 0], [0, 0, 0, 1, 0, 0, 1, 0, 0], [1, 0, 0, 1, 0, 0, 0, 1, 0]]
 
         a = factory.create(module_type="rom_base_array", cols=9, rows=8, bitmap=data, strap_spacing=4, pitch_match=True)
         self.local_check(a)

compiler/tests/05_rom_column_mux_array_test.py

@@ -0,0 +1,36 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import sys, os
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class rom_column_mux_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+
+        debug.info(1, "Testing sample for 2-way rom column_mux_array")
+        a = factory.create(module_type="rom_column_mux_array", columns=16, word_size=8)
+        self.local_check(a)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/05_rom_decoder_buffer_array_test.py

@@ -0,0 +1,37 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+
+import openram
+from openram import OPTS
+from openram.sram_factory import factory
+from openram import debug
+
+
+class rom_decoder_buffer_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+
+        debug.info(2, "Testing 4 col decoder buffer for rom decoder")
+
+
+        a = factory.create(module_type="rom_address_control_array", cols=4)
+        self.local_check(a)
+        openram.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/05_rom_decoder_test.py

@@ -25,7 +25,7 @@ class rom_decoder_test(openram_test):
         debug.info(2, "Testing 2x4 decoder for rom cell")
 
 
-        a = factory.create(module_type="rom_decoder", num_outputs=8, strap_spacing=2)
+        a = factory.create(module_type="rom_decoder", num_outputs=20, strap_spacing=2, cols=16)
         self.local_check(a)
         openram.end_openram()
 

compiler/tests/05_rom_wordline_driver_array_test.py

@@ -0,0 +1,38 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class wordline_driver_array_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+
+        # check wordline driver for single port
+        debug.info(2, "Checking driver")
+        tx = factory.create(module_type="rom_wordline_driver_array", rows=8, cols=32)
+        self.local_check(tx)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())