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column control and address precharge

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This commit is contained in:
Jacob Walker
2023-03-30 11:30:50 -07:00
parent ce8197d206
commit f7aed247fd
22 changed files with 1479 additions and 520 deletions
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compiler/modules/rom_base_array.py
+75 -126
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@@ -54,25 +54,24 @@ class rom_base_array(bitcell_base_array):
self.place_bitline_contacts()
self.place_rails()
self.route_precharge()
self.add_boundary()
self.place_rails()
self.add_label("ARRAY ZERO", self.route_layer)
self.add_label("array height", self.route_layer, [0, self.height])
#def add_pins(self):
def add_boundary(self):
ll = self.find_lowest_coords()
bottom_offset = - self.dummy.nmos.end_to_contact + self.precharge_inst.offset.y
bottom_offset = - self.zero_cell.nmos.end_to_contact + self.precharge_inst.offset.y
m1_offset = self.m1_width
self.translate_all(vector(0, ll.y + 0.5 * m1_offset))
ur = self.find_highest_coords()
ur = vector(ur.x, ur.y - self.m1_width)
#super().add_boundary(ll=vector(lowerx, lowery), ur=vector(upperx, uppery))
super().add_boundary(vector(0, 0), ur)
self.width = ur.x
self.height = ur.y
@@ -80,17 +79,9 @@ class rom_base_array(bitcell_base_array):
def add_modules(self):
# dummy cell, "dummy" cells represent 0
self.dummy = factory.create(module_type="rom_dummy_cell", route_layer=self.route_layer)
self.zero_cell = factory.create(module_name="rom_base_zero_cell", module_type="rom_base_cell", bitline_layer=self.route_layer, bit_value=0)
self.one_cell = factory.create(module_name="rom_base_one_cell", module_type="rom_base_cell", bitline_layer=self.route_layer, bit_value=1)
#base cell with no contacts
self.cell_nc = factory.create(module_name="base_mod_0_contact", module_type="rom_base_cell")
#base cell with drain contact
self.cell_dc = factory.create(module_name="base_mod_d_contact", module_type="rom_base_cell", add_drain_contact=self.route_layer)
#base cell with source contact
self.cell_sc = factory.create(module_name="base_mod_s_contact", module_type="rom_base_cell", add_source_contact=self.route_layer)
#base cell with all contacts
self.cell_ac = factory.create(module_name="base_mod_sd_contact", module_type="rom_base_cell", add_source_contact=self.route_layer, add_drain_contact=self.route_layer)
self.poly_tap = factory.create(module_type="rom_poly_tap", strap_length=self.strap_spacing)
@@ -128,98 +119,74 @@ class rom_base_array(bitcell_base_array):
# for each new strap placed, offset the column index refrenced to get correct bit in the data array
# cols are bit lines
strap_row = False
pre_strap_row = False
if row % self.strap_spacing == 0 and self.pitch_match:
strap_row = True
if (row + 1) % self.strap_spacing == 0 and self.pitch_match:
pre_strap_row = True
for col in range(self.column_size):
if col % self.strap_spacing == 0:
self.create_tap(row, col)
name = "tap_r{0}_c{1}".format(row, col)
#print("tap instance added at c{0}, r{1}".format(col, row))
self.tap_inst[row, col]=self.add_inst(name=name, mod=self.poly_tap)
self.connect_inst([])
name = "bit_r{0}_c{1}".format(row, col)
if self.data[row][col] == 1:
# if dummy/0 cell above and below a 1, add a tx with contacts on both drain and source
# if the first row and a 0 above, add both contacts
# if the last row and 0 below add both contacts
if (row < self.row_size - 1 and row > 0 and self.data[row + 1][col] == 0 and self.data[row - 1][col] == 0) or \
(row == self.row_size - 1 and self.data[row - 1][col] == 0) or \
(row == 0 and self.data[row + 1][col] == 0) or \
(row < self.row_size - 1 and self.data[row + 1][col] == 0 and strap_row) or \
(row > 0 and self.data[row - 1][col] == 0 and pre_strap_row):
new_inst = self.add_inst(name=name, mod=self.cell_ac)
# if dummy/0 is below and not above, add a source contact
# if in the first row, add a source contact
elif (row > 0 and self.data[row - 1][col] == 0) or \
(row == 0) or \
(strap_row):
new_inst=self.add_inst(name=name, mod=self.cell_sc)
elif (row < self.row_size - 1 and self.data[row + 1][col] == 0) or \
(row == self.row_size - 1) or \
(pre_strap_row):
new_inst=self.add_inst(name=name, mod=self.cell_dc)
else:
new_inst=self.add_inst(name=name, mod=self.cell_nc)
if row == self.row_size - 1 or self.get_next_cell_in_bl(row, col) == -1:
bl_l = self.int_bl_list[col]
bl_h = "gnd"
# elif first_in_col:
# bl_l = self.bitline_names[0][col]
# int_bl_list[col] = "bl_int_{0}_{1}".format(row, col)
# bl_h = int_bl_list[col]
# first_in_col = False
else:
bl_l = self.int_bl_list[col]
self.int_bl_list[col] = "bl_int_{0}_{1}".format(row, col)
bl_h = self.int_bl_list[col]
self.cell_inst[row, col] = new_inst
self.connect_inst([bl_h, bl_l, self.wordline_names[0][row], "gnd"])
else:
new_inst = self.add_inst(name=name, mod=self.dummy)
self.cell_inst[row, col] = new_inst
self.connect_inst([])
# when col = 0 bl_h is connected to vdd, otherwise connect to previous bl connection
# when col = col_size - 1 connected column_sizeto gnd otherwise create new bl connection
#
new_inst = self.create_cell(row, col)
self.cell_inst[row, col] = new_inst
row_list.append(new_inst)
name = "tap_r{0}_c{1}".format(row, self.array_col_size)
#print(*row_list)
self.tap_inst[row, self.column_size]=self.add_inst(name=name, mod=self.zero_tap)
self.tap_inst[row, 0]=self.add_inst(name=name, mod=self.zero_tap)
self.connect_inst([])
self.cell_list.append(row_list)
def create_poly_tap(self, row, col):
name = "tap_r{0}_c{1}".format(row, col)
self.tap_inst[row, col]=self.add_inst(name=name, mod=self.poly_tap)
self.connect_inst([])
def create_cell(self, row, col):
name = "bit_r{0}_c{1}".format(row, col)
# when col = 0, bl_h is connected to vdd, otherwise connect to previous bl connection
# when col = col_size - 1 connected column_sizeto gnd otherwise create new bl connection
if row == self.row_size - 1 or self.get_next_cell_in_bl(row, col) == -1:
bl_l = self.int_bl_list[col]
bl_h = "gnd"
else:
bl_l = self.int_bl_list[col]
if self.data[row][col] == 1:
self.int_bl_list[col] = "bl_int_{0}_{1}".format(row, col)
bl_h = self.int_bl_list[col]
if self.data[row][col] == 1:
new_inst = self.add_inst(name=name, mod=self.one_cell)
self.connect_inst([bl_h, bl_l, self.wordline_names[0][row], "gnd"])
else:
new_inst = self.add_inst(name=name, mod=self.zero_cell)
self.connect_inst([bl_h, self.wordline_names[0][row], "gnd"])
return new_inst
def create_precharge_inst(self):
prechrg_pins = self.bitline_names[0].copy()
for bl in range(self.column_size):
# if the internal bl was never updated there are no active cells in the bitline, so it should route straight to ground"
if self.int_bl_list[bl] == prechrg_pins[bl]:
prechrg_pins[bl] = "gnd"
# for bl in range(self.column_size):
# # if the internal bl was never updated there are no active cells in the bitline, so it should route straight to ground"
# if self.int_bl_list[bl] == prechrg_pins[bl]:
# prechrg_pins[bl] = "gnd"
prechrg_pins.append("precharge_gate")
prechrg_pins.append("vdd")
@@ -239,32 +206,21 @@ class rom_base_array(bitcell_base_array):
def place_rails(self):
spacing = self.route_pitch
self.route_horizontal_pins("D", insts=self.cell_list[self.row_size - 1])
self.copy_layout_pin(self, "D", "gnd")
rail_y = self.cell_list[self.row_size - 1][0].offset.y + self.dummy.base_width + spacing
# self.dummy.height * (self.row_size)
start_x = self.get_pin(self.bitline_names[0][0]).cx()
# self.cell_list[self.row_size - 1][0].offset.x
end_x = self.get_pin(self.bitline_names[0][self.column_size - 1]).cx()
# self.cell_list[self.row_size - 1][self.column_size - 1].offset.x
#self.dummy.height * self.row_size
#self.cell_inst[self.row_size - 1,0].uy()
rail_start = vector(start_x , rail_y)
rail_end = vector(end_x, rail_y)
def place_well_tap(self):
tap_y = self.via.uy() + drc["{0}_to_{0}".format(self.strap_layer)] * 2
self.gnd = self.add_layout_pin_rect_ends(name="gnd",
layer="m1",
start=rail_start,
end=rail_end)
for bl in range(self.column_size):
drain_pin = self.cell_list[self.row_size - 1][bl].get_pin("D")
via_pos = vector(drain_pin.cx(), rail_y)
self.add_segment_center(self.route_layer, drain_pin.center(), via_pos)
self.add_via_stack_center(via_pos, self.route_layer, "m1", ["H", "V"])
contact_pos = vector(self.via.cx(), tap_y)
self.add_via_center(layers=self.active_stack,
offset=contact_pos,
implant_type="p",
well_type="p")
self.add_power_pin(name="gnd",
loc=contact_pos,
start_layer=self.active_stack[2])
def place_array(self):
self.cell_pos = {}
@@ -274,10 +230,10 @@ class rom_base_array(bitcell_base_array):
pitch_offset = 0
for row in range(self.row_size):
if row % self.strap_spacing == 0 and row != 0 and self.pitch_match:
pitch_offset += self.poly_tap.width
# if row % self.strap_spacing == 0 and row != 0 and self.pitch_match:
# pitch_offset += self.poly_tap.width
cell_y = row * (self.dummy.height) + pitch_offset
cell_y = row * (self.zero_cell.height) + pitch_offset
cell_x = 0
for col in range(self.column_size):
@@ -285,19 +241,19 @@ class rom_base_array(bitcell_base_array):
if col % self.strap_spacing == 0:
self.strap_pos[row, col] = vector(cell_x, cell_y)
self.tap_inst[row, col].place(self.strap_pos[row, col])
cell_x += self.poly_tap.width
# cell_x += self.poly_tap.width
self.cell_pos[row, col] = vector(cell_x, cell_y)
self.cell_inst[row, col].place(self.cell_pos[row, col])
cell_x += self.dummy.width
cell_x += self.zero_cell.width
self.add_label("debug", "li", self.cell_pos[row, col])
self.strap_pos[row, self.column_size] = vector(cell_x, cell_y)
self.tap_inst[row, self.column_size].place(self.strap_pos[row, self.column_size])
self.strap_pos[row, 0] = vector(0, cell_y)
self.tap_inst[row, 0].place(self.strap_pos[row, 0])
# tap_pin = self.cell_inst[row, self.array_col_size].get_pin("poly_tap").center()
# tap_pin = self.tap_inst[row, 0].get_pin("poly_tap").center()
# self.add_layout_pin_rect_center("wl{}".format(row), "m2", tap_pin)
@@ -316,7 +272,7 @@ class rom_base_array(bitcell_base_array):
def place_precharge(self):
self.precharge_offset = vector(0, - self.precharge_inst.height - self.dummy.nmos.end_to_contact - 2 * drc["nwell_enclose_active"])
self.precharge_offset = vector(0, - self.precharge_inst.height - self.zero_cell.nmos.end_to_contact - 2 * drc["nwell_enclose_active"])
self.precharge_inst.place(offset=self.precharge_offset)
@@ -327,19 +283,12 @@ class rom_base_array(bitcell_base_array):
def place_wordline_contacts(self):
width = self.route_width
height = self.route_width
offset = vector(self.poly_contact.width * 0.5, self.dummy.poly.offset.y)
for wl in range(self.row_size):
poly_via = self.tap_inst[wl, 0].get_pin("via")
self.copy_layout_pin(self.tap_inst[wl, 0], "via", self.wordline_names[0][wl])
# self.add_via_stack_center(poly_via.center(), "m1", self.output_layer)
# self.create_horizontal_pin_bus(self.route_layer, offset=corrected_offset, names=self.wordline_names[0], pitch=self.dummy.height, length=None)
# self.create_horizontal_pin_bus(self.route_layer, offset=corrected_offset, names=self.wordline_names[0], pitch=self.zero_cell.height, length=None)
def place_bitline_contacts(self):