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replica_bitcell_array: Connect bitcells based on bitcell bl/br/wl names 

this allows us to override the bl/br/wl names of each bitcell.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2020-02-12 14:17:29 +01:00
parent f9babcf666
commit f6302caeac
2 changed files with 47 additions and 20 deletions
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26
compiler/modules/bitcell_base_array.py
View File

@ -22,6 +22,32 @@ class bitcell_base_array(design.design):
self.row_size = rows self.row_size = rows
self.column_offset = column_offset self.column_offset = column_offset
def get_all_bitline_names(self):
res = list()
bitline_names = self.cell.get_all_bitline_names()
# We have to keep the order of self.pins, otherwise we connect
# it wrong in the spice netlist
for pin in self.pins:
for bl_name in bitline_names:
if bl_name in pin:
res.append(pin)
return res
def get_all_wordline_names(self):
res = list()
wordline_names = self.cell.get_all_wl_names()
# We have to keep the order of self.pins, otherwise we connect
# it wrong in the spice netlist
for pin in self.pins:
for wl_name in wordline_names:
if wl_name in pin:
res.append(pin)
return res
def add_pins(self): def add_pins(self):
row_list = self.cell.get_all_wl_names() row_list = self.cell.get_all_wl_names()
column_list = self.cell.get_all_bitline_names() column_list = self.cell.get_all_bitline_names()

41
compiler/modules/replica_bitcell_array.py
View File

@ -138,11 +138,10 @@ class replica_bitcell_array(design.design):
def add_pins(self): def add_pins(self):
self.bitcell_array_wl_names = self.bitcell_array.get_all_wordline_names()
self.bitcell_array_bl_names = self.bitcell_array.get_all_bitline_names()
self.bitcell_array_wl_names = [x for x in self.bitcell_array.pins if x.startswith("w")] # These are the non-indexed names
self.bitcell_array_bl_names = [x for x in self.bitcell_array.pins if x.startswith("b")]
# These are the non-indexed names
self.dummy_cell_wl_names = ["dummy_"+x for x in self.cell.get_all_wl_names()] self.dummy_cell_wl_names = ["dummy_"+x for x in self.cell.get_all_wl_names()]
self.dummy_cell_bl_names = ["dummy_"+x for x in self.cell.get_all_bitline_names()] self.dummy_cell_bl_names = ["dummy_"+x for x in self.cell.get_all_bitline_names()]
self.dummy_row_bl_names = self.bitcell_array_bl_names self.dummy_row_bl_names = self.bitcell_array_bl_names
@ -316,22 +315,24 @@ class replica_bitcell_array(design.design):
# Main array wl and bl/br # Main array wl and bl/br
pin_names = self.bitcell_array.get_pin_names() pin_names = self.bitcell_array.get_pin_names()
for pin_name in pin_names: for pin_name in pin_names:
if pin_name.startswith("wl"): for wl in self.bitcell_array_wl_names:
pin_list = self.bitcell_array_inst.get_pins(pin_name) if wl in pin_name:
for pin in pin_list: pin_list = self.bitcell_array_inst.get_pins(pin_name)
self.add_layout_pin(text=pin_name, for pin in pin_list:
layer=pin.layer, self.add_layout_pin(text=pin_name,
offset=pin.ll().scale(0,1), layer=pin.layer,
width=self.width, offset=pin.ll().scale(0,1),
height=pin.height()) width=self.width,
elif pin_name.startswith("bl") or pin_name.startswith("br"): height=pin.height())
pin_list = self.bitcell_array_inst.get_pins(pin_name) for bitline in self.bitcell_array_bl_names:
for pin in pin_list: if bitline in pin_name:
self.add_layout_pin(text=pin_name, pin_list = self.bitcell_array_inst.get_pins(pin_name)
layer=pin.layer, for pin in pin_list:
offset=pin.ll().scale(1,0), self.add_layout_pin(text=pin_name,
width=pin.width(), layer=pin.layer,
height=self.height) offset=pin.ll().scale(1,0),
width=pin.width(),
height=self.height)
# Replica wordlines # Replica wordlines