Move power pins in hierarchical decoder to be further. Strap rails instead for redundant vias.

compiler/modules/hierarchical_decoder.py

@@ -548,30 +548,27 @@ class hierarchical_decoder(design.design):
     def route_vdd_gnd(self):
         """ Add a pin for each row of vdd/gnd which are must-connects next level up. """
 
-        # Find the x offsets for where the vias/pins should be placed
+        # The vias will be placed in the center and right of the cells, respectively.
-        a_xoffset = self.inv_inst[0].lx()
+        xoffset = self.nand_inst[0].cx()
-        b_xoffset = self.inv_inst[0].rx()
-        
         for num in range(0,self.rows):
-            # this will result in duplicate polygons for rails, but who cares
+            for pin_name in ["vdd", "gnd"]:
-            
+                # The nand and inv are the same height rows...
-            # Route both supplies
+                supply_pin = self.nand_inst[num].get_pin(pin_name)
-            for n in ["vdd", "gnd"]:
+                pin_pos = vector(xoffset, supply_pin.cy())
-                supply_pin = self.inv_inst[num].get_pin(n)
+                self.add_power_pin(name=pin_name,
-
+                                   loc=pin_pos)
-                # Add pins in two locations
-                for xoffset in [a_xoffset, b_xoffset]:
-                    pin_pos = vector(xoffset, supply_pin.cy())
-                    self.add_via_center(layers=("metal1", "via1", "metal2"),
-                                        offset=pin_pos,
-                                        rotate=90)
-                    self.add_via_center(layers=("metal2", "via2", "metal3"),
-                                        offset=pin_pos,
-                                        rotate=90)
-                    self.add_layout_pin_rect_center(text=n,
-                                                    layer="metal3",
-                                                    offset=pin_pos)
 
+        # Make a redundant rail too
+        for num in range(0,self.rows,2):
+            for pin_name in ["vdd", "gnd"]:
+                start = self.nand_inst[num].get_pin(pin_name).lc()
+                end = self.inv_inst[num].get_pin(pin_name).rc()
+                mid = (start+end).scale(0.5,0.5)
+                self.add_rect_center(layer="metal1",
+                                     offset=mid,
+                                     width=end.x-start.x)
+                
+                
         # Copy the pins from the predecoders
         for pre in self.pre2x4_inst + self.pre3x8_inst:
             self.copy_layout_pin(pre, "vdd")

compiler/router/router.py

@@ -774,7 +774,7 @@ class router:
                        
             # At least one of the groups must have some valid tracks
             if (len(pin_set)==0 and len(blockage_set)==0):
-                self.write_debug_gds()
+                self.write_debug_gds("blocked_pin.gds")
                 debug.error("Unable to find unblocked pin on grid.")
 
             # We need to route each of the components, so don't combine the groups
@@ -1306,8 +1306,8 @@ class router:
         """
         debug.info(0,"Adding router info")
 
-        show_blockages = False
+        show_blockages = True
-        show_blockage_grids = False
+        show_blockage_grids = True
         show_enclosures = False
         show_connectors = False
         show_all_grids = True

compiler/router/supply_router.py

@@ -65,8 +65,7 @@ class supply_router(router):
 
         # Get the pin shapes
         self.find_pins_and_blockages([self.vdd_name, self.gnd_name])
-
+        #self.write_debug_gds("pin_enclosures.gds",stop_program=False)
-        #self.write_debug_gds("pin_enclosures.gds",stop_program=True)
 
         # Add the supply rails in a mesh network and connect H/V with vias
         # Block everything