mirror of https://github.com/VLSIDA/OpenRAM.git
PEP8 cleanup, multiple vdd/gnd support
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parent
e23d41c1d4
commit
f57eeb88eb
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@ -28,7 +28,7 @@ class sense_amp_array(design.design):
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self.add_comment("words_per_row: {0}".format(words_per_row))
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self.add_comment("words_per_row: {0}".format(words_per_row))
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self.word_size = word_size
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self.word_size = word_size
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self.words_per_row = words_per_row
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self.words_per_row = words_per_row
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if not num_spare_cols:
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if not num_spare_cols:
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self.num_spare_cols = 0
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self.num_spare_cols = 0
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else:
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else:
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@ -77,7 +77,7 @@ class sense_amp_array(design.design):
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self.DRC_LVS()
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self.DRC_LVS()
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def add_pins(self):
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def add_pins(self):
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for i in range(0,self.word_size + self.num_spare_cols):
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for i in range(0, self.word_size + self.num_spare_cols):
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self.add_pin(self.data_name + "_{0}".format(i), "OUTPUT")
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self.add_pin(self.data_name + "_{0}".format(i), "OUTPUT")
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self.add_pin(self.get_bl_name() + "_{0}".format(i), "INPUT")
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self.add_pin(self.get_bl_name() + "_{0}".format(i), "INPUT")
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self.add_pin(self.get_br_name() + "_{0}".format(i), "INPUT")
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self.add_pin(self.get_br_name() + "_{0}".format(i), "INPUT")
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@ -96,7 +96,7 @@ class sense_amp_array(design.design):
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def create_sense_amp_array(self):
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def create_sense_amp_array(self):
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self.local_insts = []
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self.local_insts = []
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for i in range(0,self.word_size + self.num_spare_cols):
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for i in range(0, self.word_size + self.num_spare_cols):
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name = "sa_d{0}".format(i)
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name = "sa_d{0}".format(i)
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self.local_insts.append(self.add_inst(name=name,
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self.local_insts.append(self.add_inst(name=name,
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mod=self.amp))
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mod=self.amp))
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@ -107,14 +107,10 @@ class sense_amp_array(design.design):
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def place_sense_amp_array(self):
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def place_sense_amp_array(self):
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from tech import cell_properties
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from tech import cell_properties
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if self.bitcell.width > self.amp.width:
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amp_spacing = self.bitcell.width
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else:
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amp_spacing = self.amp.width
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for i in range(0, self.row_size, self.words_per_row):
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for i in range(0, self.row_size, self.words_per_row):
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index = int(i / self.words_per_row)
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index = int(i / self.words_per_row)
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xoffset = i * amp_spacing
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xoffset = i * self.bitcell.width
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if cell_properties.bitcell.mirror.y and (i + self.column_offset) % 2:
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if cell_properties.bitcell.mirror.y and (i + self.column_offset) % 2:
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mirror = "MY"
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mirror = "MY"
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@ -126,9 +122,9 @@ class sense_amp_array(design.design):
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self.local_insts[index].place(offset=amp_position, mirror=mirror)
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self.local_insts[index].place(offset=amp_position, mirror=mirror)
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# place spare sense amps (will share the same enable as regular sense amps)
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# place spare sense amps (will share the same enable as regular sense amps)
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for i in range(0,self.num_spare_cols):
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for i in range(0, self.num_spare_cols):
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index = self.word_size + i
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index = self.word_size + i
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xoffset = ((self.word_size * self.words_per_row) + i) * amp_spacing
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xoffset = ((self.word_size * self.words_per_row) + i) * self.bitcell.width
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if cell_properties.bitcell.mirror.y and (i + self.column_offset) % 2:
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if cell_properties.bitcell.mirror.y and (i + self.column_offset) % 2:
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mirror = "MY"
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mirror = "MY"
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@ -143,17 +139,17 @@ class sense_amp_array(design.design):
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for i in range(len(self.local_insts)):
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for i in range(len(self.local_insts)):
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inst = self.local_insts[i]
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inst = self.local_insts[i]
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gnd_pin = inst.get_pin("gnd")
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for gnd_pin in inst.get_pins("gnd"):
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self.add_power_pin(name="gnd",
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self.add_power_pin(name="gnd",
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loc=gnd_pin.center(),
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loc=gnd_pin.center(),
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start_layer=gnd_pin.layer,
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start_layer=gnd_pin.layer,
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directions=("V", "V"))
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directions=("V", "V"))
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vdd_pin = inst.get_pin("vdd")
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for vdd_pin in inst.get_pins("vdd"):
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self.add_power_pin(name="vdd",
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self.add_power_pin(name="vdd",
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loc=vdd_pin.center(),
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loc=vdd_pin.center(),
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start_layer=vdd_pin.layer,
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start_layer=vdd_pin.layer,
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directions=("V", "V"))
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directions=("V", "V"))
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bl_pin = inst.get_pin(inst.mod.get_bl_names())
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bl_pin = inst.get_pin(inst.mod.get_bl_names())
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br_pin = inst.get_pin(inst.mod.get_br_names())
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br_pin = inst.get_pin(inst.mod.get_br_names())
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