mirror of https://github.com/VLSIDA/OpenRAM.git
Add left stripe power routes to tree router as option.
This commit is contained in:
mrg
parent
d3f4810d1b
commit
f48b0b8f41
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@ -122,34 +122,44 @@ class grid:
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self.set_target(n)
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# self.set_blocked(n, False)
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def add_perimeter_target(self, side="all"):
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debug.info(3, "Adding perimeter target")
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def get_perimeter_list(self, side="left", layers=[0, 1], width=1, margin=0, offset=0):
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"""
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Side specifies which side.
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Layer specifies horizontal (0) or vertical (1)
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Width specifies how wide the perimter "stripe" should be.
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"""
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perimeter_list = []
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# Add the left/right columns
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if side=="all" or side=="left":
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x = self.ll.x
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for y in range(self.ll.y, self.ur.y, 1):
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perimeter_list.append(vector3d(x, y, 0))
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perimeter_list.append(vector3d(x, y, 1))
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for x in range(self.ll.x + offset, self.ll.x + width + offset, 1):
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for y in range(self.ll.y + margin, self.ur.y - margin, 1):
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for layer in layers:
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perimeter_list.append(vector3d(x, y, layer))
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if side=="all" or side=="right":
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x = self.ur.x
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for y in range(self.ll.y, self.ur.y, 1):
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perimeter_list.append(vector3d(x, y, 0))
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perimeter_list.append(vector3d(x, y, 1))
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for x in range(self.ur.x - width - offset, self.ur.x - offset, 1):
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for y in range(self.ll.y + margin, self.ur.y - margin, 1):
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for layer in layers:
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perimeter_list.append(vector3d(x, y, layer))
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if side=="all" or side=="bottom":
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y = self.ll.y
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for x in range(self.ll.x, self.ur.x, 1):
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perimeter_list.append(vector3d(x, y, 0))
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perimeter_list.append(vector3d(x, y, 1))
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for y in range(self.ll.y + offset, self.ll.y + width + offset, 1):
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for x in range(self.ll.x + margin, self.ur.x - margin, 1):
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for layer in layers:
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perimeter_list.append(vector3d(x, y, layer))
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if side=="all" or side=="top":
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y = self.ur.y
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for x in range(self.ll.x, self.ur.x, 1):
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perimeter_list.append(vector3d(x, y, 0))
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perimeter_list.append(vector3d(x, y, 1))
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for y in range(self.ur.y - width - offset, self.ur.y - offset, 1):
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for x in range(self.ll.x + margin, self.ur.x - margin, 1):
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for layer in layers:
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perimeter_list.append(vector3d(x, y, layer))
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return perimeter_list
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def add_perimeter_target(self, side="all", layers=[0, 1]):
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debug.info(3, "Adding perimeter target")
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perimeter_list = self.get_perimeter_list(side, layers)
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self.set_target(perimeter_list)
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@ -155,6 +155,10 @@ class pin_group:
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# Now simplify the enclosure list
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new_pin_list = self.remove_redundant_shapes(pin_list)
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# Now add the right name
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for pin in new_pin_list:
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pin.name = self.name
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debug.check(len(new_pin_list) > 0,
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"Did not find any enclosures.")
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@ -28,7 +28,7 @@ class router(router_tech):
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route on a given layer. This is limited to two layer routes.
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It populates blockages on a grid class.
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"""
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def __init__(self, layers, design, gds_filename=None, bbox=None, margin=0, route_track_width=1):
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def __init__(self, layers, design, bbox=None, margin=0, route_track_width=1):
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"""
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This will instantiate a copy of the gds file or the module at (0,0) and
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route on top of this. The blockages from the gds/module will be
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@ -39,19 +39,7 @@ class router(router_tech):
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self.cell = design
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# If didn't specify a gds blockage file, write it out to read the gds
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# This isn't efficient, but easy for now
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# start_time = datetime.now()
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if not gds_filename:
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gds_filename = OPTS.openram_temp+"temp.gds"
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self.cell.gds_write(gds_filename)
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# Load the gds file and read in all the shapes
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self.layout = gdsMill.VlsiLayout(units=GDS["unit"])
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self.reader = gdsMill.Gds2reader(self.layout)
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self.reader.loadFromFile(gds_filename)
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self.top_name = self.layout.rootStructureName
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# print_time("GDS read",datetime.now(), start_time)
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self.gds_filename = OPTS.openram_temp + "temp.gds"
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# The pin data structures
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# A map of pin names to a set of pin_layout structures
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@ -91,6 +79,16 @@ class router(router_tech):
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"""
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Initialize the ll,ur values with the paramter or using the layout boundary.
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"""
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# If didn't specify a gds blockage file, write it out to read the gds
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# This isn't efficient, but easy for now
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# Load the gds file and read in all the shapes
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self.cell.gds_write(self.gds_filename)
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self.layout = gdsMill.VlsiLayout(units=GDS["unit"])
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self.reader = gdsMill.Gds2reader(self.layout)
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self.reader.loadFromFile(self.gds_filename)
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self.top_name = self.layout.rootStructureName
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if not bbox:
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# The boundary will determine the limits to the size
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# of the routing grid
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@ -178,6 +176,17 @@ class router(router_tech):
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"""
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Find the pins and blockages in the design
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"""
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# If didn't specify a gds blockage file, write it out to read the gds
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# This isn't efficient, but easy for now
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# Load the gds file and read in all the shapes
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self.cell.gds_write(self.gds_filename)
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self.layout = gdsMill.VlsiLayout(units=GDS["unit"])
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self.reader = gdsMill.Gds2reader(self.layout)
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self.reader.loadFromFile(self.gds_filename)
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self.top_name = self.layout.rootStructureName
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# print_time("GDS read",datetime.now(), start_time)
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# This finds the pin shapes and sorts them into "groups" that
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# are connected. This must come before the blockages, so we
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# can not count the pins themselves
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@ -881,6 +890,26 @@ class router(router_tech):
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# Clearing the blockage of this pin requires the inflated pins
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self.clear_blockages(pin_name)
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def add_side_supply_pin(self, name, side="left", width=2):
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"""
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Adds a supply pin to the perimeter and resizes the bounding box.
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"""
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pg = pin_group(name, [], self)
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if name == "vdd":
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offset = width
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else:
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offset = 0
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pg.grids = set(self.rg.get_perimeter_list(side=side,
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width=width,
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margin=self.margin,
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offset=offset,
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layers=[1]))
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pg.enclosures = pg.compute_enclosures()
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pg.pins = set(pg.enclosures)
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self.cell.pin_map[name].update(pg.pins)
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self.pin_groups[name].append(pg)
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def add_perimeter_target(self, side="all"):
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"""
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This will mark all the cells on the perimeter of the original layout as a target.
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@ -1219,7 +1248,7 @@ class router(router_tech):
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""" Return the lowest, leftest pin group """
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keep_pin = None
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for index,pg in enumerate(self.pin_groups[pin_name]):
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for index, pg in enumerate(self.pin_groups[pin_name]):
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for pin in pg.enclosures:
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if not keep_pin:
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keep_pin = pin
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@ -1229,23 +1258,6 @@ class router(router_tech):
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return keep_pin
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def get_left_pins(self, pin_name):
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""" Return the leftest pin(s) group """
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keep_pins = []
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for index, pg in enumerate(self.pin_groups[pin_name]):
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for pin in pg.enclosures:
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if not keep_pins:
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keep_pins = [pin]
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else:
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# Only need to check first since they are all the same left value
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if pin.lx() == keep_pins[0].lx():
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keep_pins.append(pin)
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elif pin.lx() < keep_pins[0].lx():
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keep_pins = [pin]
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return keep_pins
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def check_all_routed(self, pin_name):
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"""
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Check that all pin groups are routed.
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@ -123,7 +123,7 @@ class router_tech:
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min_wire_width = drc("minwidth_{0}".format(layer_name), 0, math.inf)
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min_width = drc("minwidth_{0}".format(layer_name), self.route_track_width * min_wire_width, math.inf)
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min_width = self.route_track_width * drc("minwidth_{0}".format(layer_name), self.route_track_width * min_wire_width, math.inf)
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min_spacing = drc(str(layer_name)+"_to_"+str(layer_name), self.route_track_width * min_wire_width, math.inf)
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return (min_width, min_spacing)
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@ -17,7 +17,7 @@ class signal_escape_router(router):
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A router that routes signals to perimeter and makes pins.
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"""
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def __init__(self, layers, design, bbox=None, margin=0, gds_filename=None):
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def __init__(self, layers, design, bbox=None, margin=0):
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"""
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This will route on layers in design. It will get the blockages from
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either the gds file name or the design itself (by saving to a gds file).
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@ -25,7 +25,6 @@ class signal_escape_router(router):
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router.__init__(self,
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layers=layers,
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design=design,
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gds_filename=gds_filename,
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bbox=bbox,
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margin=margin)
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@ -15,12 +15,12 @@ class signal_router(router):
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route on a given layer. This is limited to two layer routes.
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"""
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def __init__(self, layers, design, gds_filename=None, bbox=None):
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def __init__(self, layers, design, bbox=None):
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"""
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This will route on layers in design. It will get the blockages from
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either the gds file name or the design itself (by saving to a gds file).
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"""
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router.__init__(self, layers, design, gds_filename, bbox)
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router.__init__(self, layers, design, bbox)
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def route(self, src, dest, detour_scale=5):
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"""
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@ -21,7 +21,7 @@ class supply_grid_router(router):
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routes a grid to connect the supply on the two layers.
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"""
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def __init__(self, layers, design, gds_filename=None, bbox=None):
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def __init__(self, layers, design, margin=0, bbox=None):
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"""
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This will route on layers in design. It will get the blockages from
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either the gds file name or the design itself (by saving to a gds file).
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@ -29,9 +29,9 @@ class supply_grid_router(router):
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start_time = datetime.now()
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# Power rail width in minimum wire widths
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self.route_track_width = 2
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self.route_track_width = 1
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router.__init__(self, layers, design, gds_filename, bbox, self.route_track_width)
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router.__init__(self, layers, design, bbox=bbox, margin=margin, route_track_width=self.route_track_width)
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# The list of supply rails (grid sets) that may be routed
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self.supply_rails = {}
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@ -357,7 +357,8 @@ class supply_grid_router(router):
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# This is inefficient since it is non-incremental, but it was
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# easier to debug.
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self.prepare_blockages(pin_name)
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self.prepare_blockages()
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self.clear_blockages(self.vdd_name)
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# Add the single component of the pin as the source
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# which unmarks it as a blockage too
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@ -369,7 +370,7 @@ class supply_grid_router(router):
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# Actually run the A* router
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if not self.run_router(detour_scale=5):
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self.write_debug_gds("debug_route.gds", False)
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self.write_debug_gds("debug_route.gds")
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# if index==3 and pin_name=="vdd":
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# self.write_debug_gds("route.gds",False)
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@ -21,7 +21,7 @@ class supply_tree_router(router):
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routes a grid to connect the supply on the two layers.
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"""
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def __init__(self, layers, design, gds_filename=None, bbox=None):
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def __init__(self, layers, design, bbox=None, side_pin=None):
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"""
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This will route on layers in design. It will get the blockages from
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either the gds file name or the design itself (by saving to a gds file).
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@ -31,11 +31,19 @@ class supply_tree_router(router):
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# for prettier routes.
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self.route_track_width = 1
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router.__init__(self, layers, design, gds_filename, bbox, self.route_track_width)
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# The pin escape router already made the bounding box big enough,
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# so we can use the regular bbox here.
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self.side_pin = side_pin
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router.__init__(self,
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layers,
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design,
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bbox=bbox,
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route_track_width=self.route_track_width)
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def route(self, vdd_name="vdd", gnd_name="gnd"):
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"""
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Route the two nets in a single layer)
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Route the two nets in a single layer.
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Setting pin stripe will make a power rail on the left side.
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"""
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debug.info(1, "Running supply router on {0} and {1}...".format(vdd_name, gnd_name))
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self.vdd_name = vdd_name
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@ -50,11 +58,17 @@ class supply_tree_router(router):
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# but this is simplest for now.
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self.create_routing_grid(signal_grid)
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# Get the pin shapes
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start_time = datetime.now()
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# Get the pin shapes
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self.find_pins_and_blockages([self.vdd_name, self.gnd_name])
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print_time("Finding pins and blockages", datetime.now(), start_time, 3)
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# Add side pins if enabled
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if self.side_pin:
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self.add_side_supply_pin(self.vdd_name)
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self.add_side_supply_pin(self.gnd_name)
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# Route the supply pins to the supply rails
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# Route vdd first since we want it to be shorter
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start_time = datetime.now()
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@ -87,15 +101,15 @@ class supply_tree_router(router):
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pin_size = len(self.pin_groups[pin_name])
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adj_matrix = [[0] * pin_size for i in range(pin_size)]
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for index1,pg1 in enumerate(self.pin_groups[pin_name]):
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for index2,pg2 in enumerate(self.pin_groups[pin_name]):
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for index1, pg1 in enumerate(self.pin_groups[pin_name]):
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for index2, pg2 in enumerate(self.pin_groups[pin_name]):
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if index1>=index2:
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continue
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dist = int(grid_utils.distance_set(list(pg1.grids)[0], pg2.grids))
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adj_matrix[index1][index2] = dist
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# Find MST
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debug.info(2, "Finding MinimumSpanning Tree")
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debug.info(2, "Finding Minimum Spanning Tree")
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X = csr_matrix(adj_matrix)
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Tcsr = minimum_spanning_tree(X)
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mst = Tcsr.toarray().astype(int)
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@ -226,14 +226,6 @@ class sram_base(design, verilog, lef):
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for inst in self.insts:
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self.copy_power_pins(inst, pin_name)
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if not OPTS.route_supplies:
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# Do not route the power supply (leave as must-connect pins)
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return
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elif OPTS.route_supplies == "grid":
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from supply_grid_router import supply_grid_router as router
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else:
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from supply_tree_router import supply_tree_router as router
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try:
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from tech import power_grid
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grid_stack = power_grid
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@ -242,14 +234,44 @@ class sram_base(design, verilog, lef):
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# Route a M3/M4 grid
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grid_stack = self.m3_stack
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rtr=router(grid_stack, self)
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# lowest_coord = self.find_lowest_coords()
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# highest_coord = self.find_highest_coords()
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# # Add two rails to the side
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# if OPTS.route_supplies == "side":
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# supply_pins = {}
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# # Find the lowest leftest pin for vdd and gnd
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# for (pin_name, pin_index) in [("vdd", 0), ("gnd", 1)]:
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# pin_width = 8 * getattr(self, "{}_width".format(grid_stack[2]))
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# pin_space = 2 * getattr(self, "{}_space".format(grid_stack[2]))
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# supply_pitch = pin_width + pin_space
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# # Add side power rails on left from bottom to top
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# # These have a temporary name and will be connected later.
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# # They are here to reserve space now and ensure other pins go beyond
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# # their perimeter.
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# supply_height = highest_coord.y - lowest_coord.y
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# supply_pins[pin_name] = self.add_layout_pin(text=pin_name,
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# layer=grid_stack[2],
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# offset=lowest_coord + vector(pin_index * supply_pitch, 0),
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# width=pin_width,
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# height=supply_height)
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if not OPTS.route_supplies:
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# Do not route the power supply (leave as must-connect pins)
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return
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elif OPTS.route_supplies == "grid":
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from supply_grid_router import supply_grid_router as router
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else:
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from supply_tree_router import supply_tree_router as router
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rtr=router(grid_stack, self, side_pin=(OPTS.route_supplies == "side"))
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rtr.route()
|
||||
|
||||
lowest_coord = self.find_lowest_coords()
|
||||
highest_coord = self.find_highest_coords()
|
||||
|
||||
if OPTS.route_supplies == "side":
|
||||
# Find the lowest leftest pin for vdd and gnd
|
||||
for (pin_name, pin_index) in [("vdd", 0), ("gnd", 1)]:
|
||||
for pin_name in ["vdd", "gnd"]:
|
||||
# Copy the pin shape(s) to rectangles
|
||||
for pin in self.get_pins(pin_name):
|
||||
self.add_rect(pin.layer,
|
||||
|
|
@ -260,43 +282,34 @@ class sram_base(design, verilog, lef):
|
|||
# Remove the pin shape(s)
|
||||
self.remove_layout_pin(pin_name)
|
||||
|
||||
# Either add two long rails or a simple pin
|
||||
if OPTS.route_supplies == "side":
|
||||
# Get the leftest pins
|
||||
pins = rtr.get_left_pins(pin_name)
|
||||
|
||||
pin_width = 2 * getattr(self, "{}_width".format(pins[0].layer))
|
||||
pin_space = 2 * getattr(self, "{}_space".format(pins[0].layer))
|
||||
supply_pitch = pin_width + pin_space
|
||||
|
||||
# Add side power rails on left from bottom to top
|
||||
# These have a temporary name and will be connected later.
|
||||
# They are here to reserve space now and ensure other pins go beyond
|
||||
# their perimeter.
|
||||
supply_height = highest_coord.y - lowest_coord.y
|
||||
supply_pin = self.add_layout_pin(text=pin_name,
|
||||
layer="m4",
|
||||
offset=lowest_coord + vector(pin_index * supply_pitch, 0),
|
||||
width=pin_width,
|
||||
height=supply_height)
|
||||
|
||||
route_width = pins[0].rx() - lowest_coord.x
|
||||
for pin in pins:
|
||||
pin_offset = vector(lowest_coord.x, pin.by())
|
||||
self.add_rect(pin.layer,
|
||||
pin_offset,
|
||||
route_width,
|
||||
pin.height())
|
||||
center_offset = vector(supply_pin.cx(),
|
||||
pin.cy())
|
||||
self.add_via_center(layers=self.m3_stack,
|
||||
offset=center_offset)
|
||||
else:
|
||||
# Get the lowest, leftest pin
|
||||
pin = rtr.get_ll_pins(pin_name)
|
||||
pin = rtr.get_ll_pin(pin_name)
|
||||
self.add_layout_pin(pin_name,
|
||||
pin.layer,
|
||||
pin.ll(),
|
||||
pin.width(),
|
||||
pin.height())
|
||||
|
||||
elif OPTS.route_supplies == "tree":
|
||||
# Update these as we may have routed outside the region (perimeter pins)
|
||||
lowest_coord = self.find_lowest_coords()
|
||||
|
||||
# Find the lowest leftest pin for vdd and gnd
|
||||
for pin_name in ["vdd", "gnd"]:
|
||||
# Copy the pin shape(s) to rectangles
|
||||
for pin in self.get_pins(pin_name):
|
||||
self.add_rect(pin.layer,
|
||||
pin.ll(),
|
||||
pin.width(),
|
||||
pin.height())
|
||||
|
||||
# Remove the pin shape(s)
|
||||
self.remove_layout_pin(pin_name)
|
||||
|
||||
# Get the lowest, leftest pin
|
||||
pin = rtr.get_ll_pin(pin_name)
|
||||
|
||||
pin_width = 2 * getattr(self, "{}_width".format(pin.layer))
|
||||
pin_space = 2 * getattr(self, "{}_space".format(pin.layer))
|
||||
|
||||
# Add it as an IO pin to the perimeter
|
||||
route_width = pin.rx() - lowest_coord.x
|
||||
|
|
@ -311,6 +324,9 @@ class sram_base(design, verilog, lef):
|
|||
pin_offset,
|
||||
pin_width,
|
||||
pin.height())
|
||||
else:
|
||||
# Grid is left with many top level pins
|
||||
pass
|
||||
|
||||
def route_escape_pins(self):
|
||||
"""
|
||||
|
|
@ -355,7 +371,7 @@ class sram_base(design, verilog, lef):
|
|||
from signal_escape_router import signal_escape_router as router
|
||||
rtr=router(layers=self.m3_stack,
|
||||
design=self,
|
||||
margin=4 * self.m3_pitch)
|
||||
margin=8 * self.m3_pitch)
|
||||
rtr.escape_route(pins_to_route)
|
||||
|
||||
def compute_bus_sizes(self):
|
||||
|
|
|
|||
Loading…
Reference in New Issue