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Abstracted LEF added. Params for array wordline layers.
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@@ -191,6 +191,11 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
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def route(self):
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global_wl_layer = layer_props.global_bitcell_array.wordline_layer
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global_wl_pitch = getattr(self, "{}_pitch".format(global_wl_layer))
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global_wl_pitch_factor = layer_props.global_bitcell_array.wordline_pitch_factor
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local_wl_layer = layer_props.local_bitcell_array.wordline_layer
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# Route the global wordlines
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for port in self.all_ports:
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if port == 0:
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@@ -200,9 +205,6 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
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wordline_pins = self.wl_array.get_inputs()
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wl_layer = layer_props.global_bitcell_array.wordline_layer
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wl_pitch = getattr(self, "{}_pitch".format(wl_layer))
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for (wl_name, in_pin_name) in zip(wordline_names, wordline_pins):
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# wl_pin = self.bitcell_array_inst.get_pin(wl_name)
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in_pin = self.wl_insts[port].get_pin(in_pin_name)
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@@ -210,23 +212,21 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
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y_offset = in_pin.cy()
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if port == 0:
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y_offset -= 2 * wl_pitch
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y_offset -= global_wl_pitch_factor * global_wl_pitch
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else:
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y_offset += 2 * wl_pitch
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self.add_layout_pin_segment_center(text=wl_name,
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layer=wl_layer,
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start=vector(self.wl_insts[port].lx(), y_offset),
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end=vector(self.wl_insts[port].lx() + self.wl_array.width, y_offset))
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y_offset += global_wl_pitch_factor * global_wl_pitch
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mid = vector(in_pin.cx(), y_offset)
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self.add_path("m2", [in_pin.center(), mid])
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self.add_layout_pin_rect_center(text=wl_name,
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layer=global_wl_layer,
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offset=mid)
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self.add_path(local_wl_layer, [in_pin.center(), mid])
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self.add_via_stack_center(from_layer=in_pin.layer,
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to_layer="m2",
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offset=in_pin.center())
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self.add_via_center(self.m2_stack,
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offset=mid)
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to_layer=local_wl_layer,
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offset=mid,
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min_area=True)
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# Route the buffers
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for port in self.all_ports:
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