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Add extra track spacings in some routes.

This commit is contained in:
Matt Guthaus 2018-09-13 14:12:24 -07:00
parent c9806feb01
commit f4389bdd8f
4 changed files with 6 additions and 8 deletions
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2
compiler/modules/control_logic.py
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@ -267,7 +267,7 @@ class control_logic(design.design):
# Connect the clock rail to the other clock rail # Connect the clock rail to the other clock rail
in_pos = self.ctrl_dff_inst.get_pin("clk").uc() in_pos = self.ctrl_dff_inst.get_pin("clk").uc()
mid_pos = in_pos + vector(0,self.m2_pitch) mid_pos = in_pos + vector(0,2*self.m2_pitch)
rail_pos = vector(self.rail_offsets["clk_buf"].x, mid_pos.y) rail_pos = vector(self.rail_offsets["clk_buf"].x, mid_pos.y)
self.add_wire(("metal1","via1","metal2"),[in_pos, mid_pos, rail_pos]) self.add_wire(("metal1","via1","metal2"),[in_pos, mid_pos, rail_pos])
self.add_via_center(layers=("metal1","via1","metal2"), self.add_via_center(layers=("metal1","via1","metal2"),

6
compiler/modules/hierarchical_predecode.py
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@ -56,8 +56,8 @@ class hierarchical_predecode(design.design):
# x offset for input inverters # x offset for input inverters
self.x_off_inv_1 = self.number_of_inputs*self.m2_pitch self.x_off_inv_1 = self.number_of_inputs*self.m2_pitch
# x offset to NAND decoder includes the left rails, mid rails and inverters, plus an extra m2 pitch # x offset to NAND decoder includes the left rails, mid rails and inverters, plus two extra m2 pitches
self.x_off_nand = self.x_off_inv_1 + self.inv.width + (2*self.number_of_inputs + 1) * self.m2_pitch self.x_off_nand = self.x_off_inv_1 + self.inv.width + (2*self.number_of_inputs + 2) * self.m2_pitch
# x offset to output inverters # x offset to output inverters
self.x_off_inv_2 = self.x_off_nand + self.nand.width self.x_off_inv_2 = self.x_off_nand + self.nand.width
@ -78,7 +78,7 @@ class hierarchical_predecode(design.design):
invert_names = ["Abar[{}]".format(x) for x in range(self.number_of_inputs)] invert_names = ["Abar[{}]".format(x) for x in range(self.number_of_inputs)]
non_invert_names = ["A[{}]".format(x) for x in range(self.number_of_inputs)] non_invert_names = ["A[{}]".format(x) for x in range(self.number_of_inputs)]
decode_names = invert_names + non_invert_names decode_names = invert_names + non_invert_names
offset = vector(self.x_off_inv_1 + self.inv.width + self.m2_pitch, 2*self.m1_width) offset = vector(self.x_off_inv_1 + self.inv.width + 2*self.m2_pitch, 2*self.m1_width)
self.decode_rails = self.create_vertical_bus(layer="metal2", self.decode_rails = self.create_vertical_bus(layer="metal2",
pitch=self.m2_pitch, pitch=self.m2_pitch,
offset=offset, offset=offset,

2
technology/scn3me_subm/tech/tech.py
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@ -174,7 +174,7 @@ drc["metal2_enclosure_via2"] = _lambda_
# Not a rule # Not a rule
drc["minarea_metal2"] = 0 drc["minarea_metal2"] = 0
# 14.2 Exact size # 14.1 Exact size
drc["minwidth_via2"] = 2*_lambda_ drc["minwidth_via2"] = 2*_lambda_
# 14.2 Minimum spacing # 14.2 Minimum spacing
drc["via2_to_via2"] = 3*_lambda_ drc["via2_to_via2"] = 3*_lambda_

4
technology/scn4m_subm/tech/tech.py
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@ -189,8 +189,6 @@ drc["metal3_to_metal3"] = 3*_lambda_
drc["metal3_extend_via2"] = _lambda_ drc["metal3_extend_via2"] = _lambda_
# Reserved for asymmetric enclosures # Reserved for asymmetric enclosures
drc["metal3_enclosure_via2"] = _lambda_ drc["metal3_enclosure_via2"] = _lambda_
# Reserved for asymmetric enclosures
drc["metal2_enclosure_via1"] = _lambda_
# 21.3 Minimum overlap by metal3 # 21.3 Minimum overlap by metal3
drc["metal3_extend_via3"] = _lambda_ drc["metal3_extend_via3"] = _lambda_
# Reserved for asymmetric enclosures # Reserved for asymmetric enclosures
@ -212,7 +210,7 @@ drc["metal4_extend_via3"] = 2*_lambda_
# Reserved for asymmetric enclosures # Reserved for asymmetric enclosures
drc["metal4_enclosure_via3"] = 2*_lambda_ drc["metal4_enclosure_via3"] = 2*_lambda_
# Not a rule # Not a rule
drc["minarea_metal3"] = 0 drc["minarea_metal4"] = 0
################################################### ###################################################
##END DRC/LVS Rules ##END DRC/LVS Rules