Merge branch 'singleport_refactor' into array_gen

compiler/modules/write_mask_and_array.py

@@ -11,6 +11,7 @@ from openram.base import design
 from openram.base import vector
 from openram.sram_factory import factory
 from openram import OPTS
+from openram.tech import drc
 
 
 class write_mask_and_array(design):
@@ -104,6 +105,10 @@ class write_mask_and_array(design):
             base = vector(self.offsets[int(i * write_bits)], 0)
             self.and2_insts[i].place(base)
 
+        # decide whethre to connect nwell to avoid drc errors
+        if self.bitcell.width < drc("nwell_to_nwell"):
+            self.and2.extend_wells(width=self.and2.width + drc("nwell_to_nwell"))
+        
     def add_layout_pins(self):
 
         # Create the enable pin that connects all write mask AND array's B pins