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Merge branch 'singleport_refactor' into array_gen
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@@ -12,10 +12,11 @@ class row_cap_array(bitcell_base_array):
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"""
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Generate a dummy row/column for the replica array.
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"""
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def __init__(self, rows, cols, column_offset=0, mirror=0, name=""):
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def __init__(self, rows, cols, column_offset=0, mirror=0, location="", name=""):
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super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
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self.mirror = mirror
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self.no_instances = True
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self.location = location
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#self.no_instances = True
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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@@ -69,44 +70,21 @@ class row_cap_array(bitcell_base_array):
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return bitcell_pins
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def place_array(self, name_template, row_offset=0):
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xoffset = 0.0
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for col in range(self.column_size):
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yoffset = self.cell.height
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tempx, dir_y = self._adjust_x_offset(xoffset, col, self.column_offset)
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for row in range(self.row_size):
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tempy, dir_x = self._adjust_y_offset(yoffset, row + 1, row_offset)
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if dir_x and dir_y:
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dir_key = "XY"
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elif dir_x:
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dir_key = "MX"
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elif dir_y:
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dir_key = "MY"
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else:
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dir_key = ""
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self.cell_inst[row, col].place(offset=[tempx, tempy],
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mirror=dir_key)
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yoffset += self.cell.height
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xoffset += self.cell.width
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def add_layout_pins(self):
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""" Add the layout pins """
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row_list = self.cell.get_all_wl_names()
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for row in range(1, self.row_size - 1):
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for cell_row in row_list:
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wl_pin = self.cell_inst[row, 0].get_pin(cell_row)
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self.add_layout_pin(text=cell_row + "_{0}".format(row),
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wl_names = self.cell.get_all_wl_names()
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max_row = self.row_size - 2
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for row in range(0, max_row):
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for port in self.all_ports:
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wl_pin = self.cell_inst[max_row - 1 - row, 0].get_pin(wl_names[port])
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self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
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layer=wl_pin.layer,
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offset=wl_pin.ll().scale(0, 1),
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width=self.width,
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height=wl_pin.height())
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for row in range(1, self.row_size - 1):
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for row in range(0, max_row):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vdd", "gnd"]:
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