Convert entire OpenRAM to use python3. Works with Python 3.6.

Major changes:
Remove mpmath library and use numpy instead.
Convert bytes to new bytearrays.
Fix class name check for duplicate gds instances.
Add explicit integer conversion from floats.
Fix importlib reload from importlib library
Fix new key/index syntax issues.
Fix filter and map conversion to lists.
Fix deprecation warnings.
Fix Circuits vs Netlist in Magic LVS results.
Fix file closing warnings.

compiler/pgates/pinv.py

@@ -17,6 +17,7 @@ class pinv(pgate.pgate):
     from center of rail to rail..  The route_output will route the
     output to the right side of the cell for easier access.
     """
+    from importlib import reload
     c = reload(__import__(OPTS.bitcell))
     bitcell = getattr(c, OPTS.bitcell)
 

compiler/pgates/pinvbuf.py

@@ -11,6 +11,7 @@ class pinvbuf(design.design):
     This is a simple inverter/buffer used for driving loads. It is
     used in the column decoder for 1:2 decoding and as the clock buffer.
     """
+    from importlib import reload
     c = reload(__import__(OPTS.bitcell))
     bitcell = getattr(c, OPTS.bitcell)
 

compiler/pgates/pnand2.py

@@ -12,6 +12,7 @@ class pnand2(pgate.pgate):
     This model use ptx to generate a 2-input nand within a cetrain height.
     """
 
+    from importlib import reload
     c = reload(__import__(OPTS.bitcell))
     bitcell = getattr(c, OPTS.bitcell)
 

compiler/pgates/pnand3.py

@@ -12,6 +12,7 @@ class pnand3(pgate.pgate):
     This model use ptx to generate a 2-input nand within a cetrain height.
     """
 
+    from importlib import reload
     c = reload(__import__(OPTS.bitcell))
     bitcell = getattr(c, OPTS.bitcell)
 

compiler/pgates/pnor2.py

@@ -12,6 +12,7 @@ class pnor2(pgate.pgate):
     This model use ptx to generate a 2-input nor within a cetrain height.
     """
 
+    from importlib import reload
     c = reload(__import__(OPTS.bitcell))
     bitcell = getattr(c, OPTS.bitcell)
 

compiler/pgates/precharge.py

@@ -16,6 +16,7 @@ class precharge(pgate.pgate):
         pgate.pgate.__init__(self, name)
         debug.info(2, "create single precharge cell: {0}".format(name))
 
+        from importlib import reload
         c = reload(__import__(OPTS.bitcell))
         self.mod_bitcell = getattr(c, OPTS.bitcell)
         self.bitcell = self.mod_bitcell()

compiler/pgates/ptx.py

@@ -4,7 +4,6 @@ from tech import drc, info, spice
 from vector import vector
 from contact import contact
 import path
-import re
 
 class ptx(design.design):
     """
@@ -28,7 +27,7 @@ class ptx(design.design):
         if num_contacts:
             name += "_c{}".format(num_contacts)
         # replace periods with underscore for newer spice compatibility
-        name=re.sub('\.','_',name)
+        name=name.replace('.','_')
 
         design.design.__init__(self, name)
         debug.info(3, "create ptx2 structure {0}".format(name))

compiler/pgates/single_level_column_mux.py

@@ -17,6 +17,7 @@ class single_level_column_mux(design.design):
         design.design.__init__(self, name)
         debug.info(2, "create single column mux cell: {0}".format(name))
 
+        from importlib import reload
         c = reload(__import__(OPTS.bitcell))
         self.mod_bitcell = getattr(c, OPTS.bitcell)
         self.bitcell = self.mod_bitcell()