Convert entire OpenRAM to use python3. Works with Python 3.6.

Major changes:
Remove mpmath library and use numpy instead.
Convert bytes to new bytearrays.
Fix class name check for duplicate gds instances.
Add explicit integer conversion from floats.
Fix importlib reload from importlib library
Fix new key/index syntax issues.
Fix filter and map conversion to lists.
Fix deprecation warnings.
Fix Circuits vs Netlist in Magic LVS results.
Fix file closing warnings.

compiler/base/design.py

@@ -29,18 +29,18 @@ class design(hierarchy_spice.spice, hierarchy_layout.layout):
         # because each reference must be a unique name.
         # These modules ensure unique names or have no changes if they
         # aren't unique
-        ok_list = ['ms_flop.ms_flop',
-                   'dff.dff',
-                   'dff_buf.dff_buf',
-                   'bitcell.bitcell',
-                   'contact.contact',
-                   'ptx.ptx',
-                   'sram.sram',
-                   'hierarchical_predecode2x4.hierarchical_predecode2x4',
-                   'hierarchical_predecode3x8.hierarchical_predecode3x8']
+        ok_list = ['ms_flop',
+                   'dff',
+                   'dff_buf',
+                   'bitcell',
+                   'contact',
+                   'ptx',
+                   'sram',
+                   'hierarchical_predecode2x4',
+                   'hierarchical_predecode3x8']
         if name not in design.name_map:
             design.name_map.append(name)
-        elif str(self.__class__) in ok_list:
+        elif self.__class__.__name__ in ok_list:
             pass
         else:
             debug.error("Duplicate layout reference name {0} of class {1}. GDS2 requires names be unique.".format(name,self.__class__),-1)

compiler/base/hierarchy_spice.py

@@ -116,10 +116,11 @@ class spice(verilog.verilog):
             self.spice = f.readlines()
             for i in range(len(self.spice)):
                 self.spice[i] = self.spice[i].rstrip(" \n")
+            f.close()
 
             # find the correct subckt line in the file
             subckt = re.compile("^.subckt {}".format(self.name), re.IGNORECASE)
-            subckt_line = filter(subckt.search, self.spice)[0]
+            subckt_line = list(filter(subckt.search, self.spice))[0]
             # parses line into ports and remove subckt
             self.pins = subckt_line.split(" ")[2:]
         else:

compiler/base/pin_layout.py

@@ -20,7 +20,7 @@ class pin_layout:
         self.rect = [x.snap_to_grid() for x in self.rect]
         # if it's a layer number look up the layer name. this assumes a unique layer number.
         if type(layer_name_num)==int:
-            self.layer = layer.keys()[layer.values().index(layer_name_num)]
+            self.layer = list(layer.keys())[list(layer.values()).index(layer_name_num)]
         else:
             self.layer=layer_name_num
         self.layer_num = layer[self.layer]