mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-31 18:25:18 +02:00
Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.
This commit is contained in:
@@ -24,13 +24,6 @@ class precharge_test(unittest.TestCase):
|
||||
import precharge_array
|
||||
import tech
|
||||
|
||||
debug.info(2, "Checking 1 column precharge")
|
||||
OPTS.check_lvsdrc = False
|
||||
pc = precharge_array.precharge_array(
|
||||
name="precharge_array", columns=1, ptx_width=tech.drc["minwidth_tx"], beta=2)
|
||||
OPTS.check_lvsdrc = True
|
||||
self.local_check(pc)
|
||||
|
||||
debug.info(2, "Checking 3 column precharge")
|
||||
OPTS.check_lvsdrc = False
|
||||
pc = precharge_array.precharge_array(
|
||||
|
||||
Reference in New Issue
Block a user