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Use non-channel route for s8 port_data

This commit is contained in:
mrg 2020-06-02 11:43:57 -07:00
parent 45b0601e4b
commit f1b7b91b1a
1 changed files with 25 additions and 10 deletions
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33
compiler/modules/port_data.py
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@ -180,6 +180,7 @@ class port_data(design.design):
# Precharge will be shifted left if needed # Precharge will be shifted left if needed
self.precharge_array = factory.create(module_type="precharge_array", self.precharge_array = factory.create(module_type="precharge_array",
columns=self.num_cols + 1, columns=self.num_cols + 1,
port=self.port,
bitcell_bl=self.bl_names[self.port], bitcell_bl=self.bl_names[self.port],
bitcell_br=self.br_names[self.port]) bitcell_br=self.br_names[self.port])
self.add_mod(self.precharge_array) self.add_mod(self.precharge_array)
@ -250,6 +251,7 @@ class port_data(design.design):
# module, which happens before we create the real precharge_array # module, which happens before we create the real precharge_array
self.precharge_array = factory.create(module_type="precharge_array", self.precharge_array = factory.create(module_type="precharge_array",
columns=self.num_cols + 1, columns=self.num_cols + 1,
port=self.port,
bitcell_bl=self.bl_names[self.port], bitcell_bl=self.bl_names[self.port],
bitcell_br=self.br_names[self.port]) bitcell_br=self.br_names[self.port])
@ -536,11 +538,18 @@ class port_data(design.design):
# This could be a channel route, but in some techs the bitlines # This could be a channel route, but in some techs the bitlines
# are too close together. # are too close together.
self.channel_route_bitlines(inst1=inst1, if OPTS.tech_name == "s8":
inst1_bls_template=inst1_bls_templ, self.connect_bitlines(inst1=inst1,
inst2=inst2, inst1_bls_template=inst1_bls_templ,
num_bits=self.word_size, inst2=inst2,
inst1_start_bit=start_bit) num_bits=self.word_size,
inst1_start_bit=start_bit)
else:
self.channel_route_bitlines(inst1=inst1,
inst1_bls_template=inst1_bls_templ,
inst2=inst2,
num_bits=self.word_size,
inst1_start_bit=start_bit)
def route_write_driver_to_column_mux_or_precharge_array(self, port): def route_write_driver_to_column_mux_or_precharge_array(self, port):
""" Routing of BL and BR between sense_amp and column mux or precharge array """ """ Routing of BL and BR between sense_amp and column mux or precharge array """
@ -562,10 +571,16 @@ class port_data(design.design):
# This could be a channel route, but in some techs the bitlines # This could be a channel route, but in some techs the bitlines
# are too close together. # are too close together.
self.channel_route_bitlines(inst1=inst1, inst2=inst2, if OPTS.tech_name == "s8":
num_bits=self.word_size, self.connect_bitlines(inst1=inst1, inst2=inst2,
inst1_bls_template=inst1_bls_templ, num_bits=self.word_size,
inst1_start_bit=start_bit) inst1_bls_template=inst1_bls_templ,
inst1_start_bit=start_bit)
else:
self.channel_route_bitlines(inst1=inst1, inst2=inst2,
num_bits=self.word_size,
inst1_bls_template=inst1_bls_templ,
inst1_start_bit=start_bit)
def route_write_driver_to_sense_amp(self, port): def route_write_driver_to_sense_amp(self, port):
""" Routing of BL and BR between write driver and sense amp """ """ Routing of BL and BR between write driver and sense amp """