mirror of https://github.com/VLSIDA/OpenRAM.git
Netlist only in verilog test
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1d5e5e3607
commit
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@ -21,7 +21,7 @@ class verilog_test(openram_test):
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globals.init_openram(config_file)
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globals.init_openram(config_file)
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OPTS.route_supplies=False
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OPTS.route_supplies=False
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OPTS.check_lvsdrc=False
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OPTS.check_lvsdrc=False
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OPTS.netlist_only=True
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from sram import sram
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from sram import sram
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from sram_config import sram_config
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from sram_config import sram_config
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c = sram_config(word_size=2,
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c = sram_config(word_size=2,
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