Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport

compiler/base/hierarchy_layout.py

@@ -718,7 +718,7 @@ class layout(lef.lef):
         conflicts between pins.
         """
 
-        def remove_pin_from_graph(pin, g):
+        def remove_net_from_graph(pin, g):
             # Remove the pin from the keys
             g.pop(pin,None)
             # Remove the pin from all conflicts
@@ -726,7 +726,8 @@ class layout(lef.lef):
             for other_pin,conflicts in g.items():
                 if pin in conflicts:
                     conflicts.remove(pin)
-                    vcg[other_pin]=conflicts
+                    g[other_pin]=conflicts
+            return g
 
         if not pitch:
             pitch = self.m2_pitch
@@ -740,20 +741,24 @@ class layout(lef.lef):
         
         # Initialize the vertical conflict graph (vcg) and make a list of all pins
         vcg = {}
-        for (top_name, bot_name) in route_map:
-            vcg[top_name] = []
-            vcg[bot_name] = []
         
         # Find the vertical pin conflicts
         # FIXME: O(n^2) but who cares for now
         for top_name,top_pin in top_pins.items():
+            vcg[top_name]=[]    
             for bot_name,bot_pin in bottom_pins.items():
-                if not vertical and abs(top_pin.center().x-bot_pin.center().x) < pitch:
+                # Remember, vertical is the boolean of the routes in the channel
-                    vcg[top_name].append(bot_name)
+                # so check the intervals of the pins in the other dimension
-                    vcg[bot_name].append(top_name)                    
+                x_overlap = abs(top_pin.center().x-bot_pin.center().x)<pitch
-                elif vertical and abs(top_pin.center().y-bot_pin.center().y) < pitch:
+                y_overlap = abs(top_pin.center().y-bot_pin.center().y)<pitch
-                    vcg[top_name].append(bot_name)
+                             
-                    vcg[bot_name].append(top_name)
+                if (vertical and y_overlap) or (not vertical and x_overlap):
+                    try:
+                        vcg[bot_name].append(top_name)
+                    except:
+                        vcg[bot_name] = [top_name]
+                    
+        #FIXME: What if we have a cycle? 
 
         # This is the starting offset of the first trunk
         if vertical:
@@ -770,7 +775,7 @@ class layout(lef.lef):
             route_pin=None
             for route_pin,conflicts in vcg.items():
                 if len(conflicts)==0:
-                    remove_pin_from_graph(route_pin,vcg)
+                    vcg=remove_net_from_graph(route_pin,vcg)
                     break
 
             # Get the connected pins from the routing map
@@ -781,7 +786,7 @@ class layout(lef.lef):
             
             # Remove the other pins from the conflict graph too
             for other_pin in pin_connections:
-                remove_pin_from_graph(other_pin, vcg)
+                vcg=remove_net_from_graph(other_pin, vcg)
                 
             # Create a list of the pins rather than a list of the names
             pin_list = [all_pins[pin_name] for pin_name in pin_connections]

compiler/verify/magic.py

@@ -78,6 +78,7 @@ def write_magic_script(cell_name, gds_name, extract=False):
     f = open(run_file, "w")
     f.write("#!/bin/sh\n")
     f.write("{} -dnull -noconsole << EOF\n".format(OPTS.drc_exe[1]))
+    f.write("path sys +{}/tech\n".format(OPTS.openram_tech))
     f.write("tech load SCN3ME_SUBM.30\n")
     #gf.write("scalegrid 1 8\n")
     #f.write("gds rescale no\n")

technology/scn3me_subm/tech/LICENSE.txt

@@ -0,0 +1,10 @@
+The file SCN3ME_SUBM.30.tech is from qflow 1.2 and has the following
+license information:
+---------------------------------------------------------------
+Tim Edwards
+Open Circuit Design
+v1.0 April 2013
+v1.1 May   2015
+v1.2 April 2017
+---------------------------------------------------------------
+GPL Copyright (c) 2017