add no rbl support to port address

compiler/modules/port_address.py

@@ -18,11 +18,12 @@ class port_address(design):
     Create the address port (row decoder and wordline driver)..
     """
 
-    def __init__(self, cols, rows, port, name=""):
+    def __init__(self, cols, rows, port, has_rbl, name=""):
 
         self.num_cols = cols
         self.num_rows = rows
         self.port = port
+        self.has_rbl = has_rbl
         self.addr_size = ceil(log(self.num_rows, 2))
 
         if name == "":
@@ -41,6 +42,7 @@ class port_address(design):
         self.add_modules()
         self.create_row_decoder()
         self.create_wordline_driver()
+        if self.has_rbl:
             self.create_rbl_driver()
 
     def create_layout(self):
@@ -63,6 +65,7 @@ class port_address(design):
         for bit in range(self.num_rows):
             self.add_pin("wl_{0}".format(bit), "OUTPUT")
 
+        if self.has_rbl:
             self.add_pin("rbl_wl", "OUTPUT")
 
         self.add_pin("vdd", "POWER")
@@ -76,6 +79,7 @@ class port_address(design):
 
     def route_supplies(self):
         """ Propagate all vdd/gnd pins up to this level for all modules """
+        if self.has_rbl:
             if layer_props.wordline_driver.vertical_supply:
                 self.copy_layout_pin(self.rbl_driver_inst, "vdd")
             else:
@@ -90,6 +94,7 @@ class port_address(design):
         self.copy_layout_pin(self.row_decoder_inst, "gnd")
 
         # Also connect the B input of the RBL and_dec to vdd
+        if self.has_rbl:
             if OPTS.local_array_size == 0:
                 rbl_b_pin = self.rbl_driver_inst.get_pin("B")
                 rbl_loc = rbl_b_pin.center() - vector(3 * self.m1_pitch, 0)
@@ -105,6 +110,7 @@ class port_address(design):
             driver_name = "wl_{}".format(row)
             self.copy_layout_pin(self.wordline_driver_array_inst, driver_name)
 
+        if self.has_rbl:
             self.copy_layout_pin(self.rbl_driver_inst, "Z", "rbl_wl")
 
     def route_internal(self):
@@ -125,6 +131,7 @@ class port_address(design):
                                       offset=driver_in_pos)
 
         # Route the RBL from the enable input
+        if self.has_rbl:
             en_pin = self.wordline_driver_array_inst.get_pin("en")
             if self.port == 0:
                 en_pos = en_pin.bc()
@@ -164,6 +171,7 @@ class port_address(design):
         # to compensate for the local array inverters
         b = factory.create(module_type=OPTS.bitcell)
 
+        if self.has_rbl:
             if local_array_size > 0:
                 # The local wordline driver will change the polarity
                 self.rbl_driver = factory.create(module_type="inv_dec",
@@ -231,6 +239,7 @@ class port_address(design):
         wordline_driver_array_offset = vector(self.row_decoder_inst.rx(), 0)
         self.wordline_driver_array_inst.place(wordline_driver_array_offset)
 
+        if self.has_rbl:
             # This m4_pitch corresponds to the offset space for jog routing in the
             # wordline_driver_array
             rbl_driver_offset = wordline_driver_array_offset + vector(2 * self.m4_pitch, 0)