Reabstracting bit and word line names.

compiler/modules/bitcell_array.py

@@ -13,9 +13,8 @@ from sram_factory import factory
 
 class bitcell_array(bitcell_base_array):
     """
-    Creates a rows x cols array of memory cells. Assumes bit-lines
+    Creates a rows x cols array of memory cells.
-    and word line is connected by abutment.
+    Assumes bit-lines and word lines are connected by abutment.
-    Connects the word lines and bit lines.
     """
     def __init__(self, rows, cols, column_offset=0, name=""):
         super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
@@ -27,7 +26,7 @@ class bitcell_array(bitcell_base_array):
         # We don't offset this because we need to align
         # the replica bitcell in the control logic
         # self.offset_all_coordinates()
-        
+
     def create_netlist(self):
         """ Create and connect the netlist """
         self.add_modules()
@@ -41,7 +40,7 @@ class bitcell_array(bitcell_base_array):
         self.add_layout_pins()
 
         self.add_boundary()
-        
+
         self.DRC_LVS()
 
     def add_modules(self):
@@ -58,20 +57,20 @@ class bitcell_array(bitcell_base_array):
                 self.cell_inst[row, col]=self.add_inst(name=name,
                                                        mod=self.cell)
                 self.connect_inst(self.get_bitcell_pins(row, col))
-                
+
     def analytical_power(self, corner, load):
         """Power of Bitcell array and bitline in nW."""
-        
+
         # Dynamic Power from Bitline
         bl_wire = self.gen_bl_wire()
         cell_load = 2 * bl_wire.return_input_cap()
         bl_swing = OPTS.rbl_delay_percentage
         freq = spice["default_event_frequency"]
         bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
-        
+
         # Calculate the bitcell power which currently only includes leakage
         cell_power = self.cell.analytical_power(corner, load)
-        
+
         # Leakage power grows with entire array and bitlines.
         total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
                                         cell_power.leakage * self.column_size * self.row_size)
@@ -83,7 +82,8 @@ class bitcell_array(bitcell_base_array):
         else:
             width = self.width
         wl_wire = self.generate_rc_net(int(self.column_size), width, drc("minwidth_m1"))
-        wl_wire.wire_c = 2 * spice["min_tx_gate_c"] + wl_wire.wire_c # 2 access tx gate per cell
+        # 2 access tx gate per cell
+        wl_wire.wire_c = 2 * spice["min_tx_gate_c"] + wl_wire.wire_c
         return wl_wire
 
     def gen_bl_wire(self):
@@ -93,7 +93,8 @@ class bitcell_array(bitcell_base_array):
             height = self.height
         bl_pos = 0
         bl_wire = self.generate_rc_net(int(self.row_size - bl_pos), height, drc("minwidth_m1"))
-        bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
+        # 1 access tx d/s per cell
+        bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c
         return bl_wire
 
     def get_wordline_cin(self):
@@ -102,7 +103,7 @@ class bitcell_array(bitcell_base_array):
         bitcell_wl_cin = self.cell.get_wl_cin()
         total_cin = bitcell_wl_cin * self.column_size
         return total_cin
-        
+
     def graph_exclude_bits(self, targ_row, targ_col):
         """Excludes bits in column from being added to graph except target"""
         # Function is not robust with column mux configurations
@@ -111,7 +112,7 @@ class bitcell_array(bitcell_base_array):
                 if row == targ_row and col == targ_col:
                     continue
                 self.graph_inst_exclude.add(self.cell_inst[row, col])
-            
+
     def get_cell_name(self, inst_name, row, col):
         """Gets the spice name of the target bitcell."""
         return inst_name + '.x' + self.cell_inst[row, col].name, self.cell_inst[row, col]

compiler/modules/bitcell_base_array.py

@@ -8,6 +8,7 @@
 import debug
 import design
 from tech import cell_properties
+from sram_factory import factory
 
 
 class bitcell_base_array(design.design):
@@ -15,7 +16,7 @@ class bitcell_base_array(design.design):
     Abstract base class for bitcell-arrays -- bitcell, dummy, replica
     """
     def __init__(self, name, rows, cols, column_offset):
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
         self.add_comment("rows: {0} cols: {1}".format(rows, cols))
 
@@ -23,41 +24,40 @@ class bitcell_base_array(design.design):
         self.row_size = rows
         self.column_offset = column_offset
 
-    def get_all_bitline_names(self):
+        # Bitcell for port names only
+        self.cell = factory.create(module_type="bitcell")
+        
+        self.create_all_bitline_names()
+        self.create_all_wordline_names()
 
-        res = list()
+    def get_all_bitline_names(self, prefix=""):
+        return [prefix + x for x in self.bitline_names]
+
+    def create_all_bitline_names(self):
+        self.bitline_names = list()
         bitline_names = self.cell.get_all_bitline_names()
 
-        # We have to keep the order of self.pins, otherwise we connect
+        for col in range(self.column_size):
-        # it wrong in the spice netlist
+            for cell_column in bitline_names:
-        for pin in self.pins:
+                self.bitline_names.append("{0}_{1}".format(cell_column, col))
-            for bl_name in bitline_names:
-                if bl_name in pin:
-                    res.append(pin)
-        return res
 
-    def get_all_wordline_names(self):
+    def get_all_wordline_names(self, prefix=""):
+        return [prefix + x for x in self.wordline_names]
 
-        res = list()
+    def create_all_wordline_names(self):
+
+        self.wordline_names = list()
         wordline_names = self.cell.get_all_wl_names()
 
-        # We have to keep the order of self.pins, otherwise we connect
+        for row in range(self.row_size):
-        # it wrong in the spice netlist
+            for cell_row in wordline_names:
-        for pin in self.pins:
+                self.wordline_names.append("{0}_{1}".format(cell_row, row))
-            for wl_name in wordline_names:
-                if wl_name in pin:
-                    res.append(pin)
-        return res
 
     def add_pins(self):
-        row_list = self.cell.get_all_wl_names()
+        for bl_name in self.bitline_names:
-        column_list = self.cell.get_all_bitline_names()
+            self.add_pin(bl_name, "INOUT")
-        for col in range(self.column_size):
+        for wl_name in self.wordline_names:
-            for cell_column in column_list:
+            self.add_pin(wl_name, "INPUT")
-                self.add_pin(cell_column+"_{0}".format(col), "INOUT")
-        for row in range(self.row_size):
-            for cell_row in row_list:
-                    self.add_pin(cell_row+"_{0}".format(row), "INPUT")
         self.add_pin("vdd", "POWER")
         self.add_pin("gnd", "GROUND")
 
@@ -66,13 +66,10 @@ class bitcell_base_array(design.design):
         indexed by column and row, for instance use in bitcell_array """
 
         bitcell_pins = []
-
+        # bitlines
-        pin_names = self.cell.get_all_bitline_names()
+        bitcell_pins.extend([x for x in self.bitline_names if x.endswith("_{0}".format(col))])
-        for pin in pin_names:
+        # wordlines
-            bitcell_pins.append(pin + "_{0}".format(col))
+        bitcell_pins.extend([x for x in self.wordline_names if x.endswith("_{0}".format(row))])
-        pin_names = self.cell.get_all_wl_names()
-        for pin in pin_names:
-            bitcell_pins.append(pin + "_{0}".format(row))
         bitcell_pins.append("vdd")
         bitcell_pins.append("gnd")
 
@@ -81,22 +78,21 @@ class bitcell_base_array(design.design):
     def add_layout_pins(self):
         """ Add the layout pins """
 
-        row_list = self.cell.get_all_wl_names()
+        bitline_names = self.cell.get_all_bitline_names()
-        column_list = self.cell.get_all_bitline_names()
-
         for col in range(self.column_size):
-            for cell_column in column_list:
+            for bl_name in bitline_names:
-                bl_pin = self.cell_inst[0, col].get_pin(cell_column)
+                bl_pin = self.cell_inst[0, col].get_pin(bl_name)
-                self.add_layout_pin(text=cell_column + "_{0}".format(col),
+                self.add_layout_pin(text="{0}_{1}".format(bl_name, col),
                                     layer=bl_pin.layer,
                                     offset=bl_pin.ll().scale(1, 0),
                                     width=bl_pin.width(),
                                     height=self.height)
 
+        wl_names = self.cell.get_all_wl_names()
         for row in range(self.row_size):
-            for cell_row in row_list:
+            for wl_name in wl_names:
-                wl_pin = self.cell_inst[row, 0].get_pin(cell_row)
+                wl_pin = self.cell_inst[row, 0].get_pin(wl_name)
-                self.add_layout_pin(text=cell_row + "_{0}".format(row),
+                self.add_layout_pin(text="{0}_{1}".format(wl_name, row),
                                     layer=wl_pin.layer,
                                     offset=wl_pin.ll().scale(0, 1),
                                     width=self.width,

compiler/modules/local_bitcell_array.py

@@ -8,6 +8,7 @@
 import design
 from globals import OPTS
 from sram_factory import factory
+import debug
 
 
 class local_bitcell_array(design.design):
@@ -26,7 +27,7 @@ class local_bitcell_array(design.design):
         self.left_rbl = left_rbl
         self.right_rbl = right_rbl
         self.all_ports = ports
-        
+
         self.create_netlist()
         if not OPTS.netlist_only:
             self.create_layout()
@@ -34,7 +35,7 @@ class local_bitcell_array(design.design):
         # We don't offset this because we need to align
         # the replica bitcell in the control logic
         # self.offset_all_coordinates()
-        
+
     def create_netlist(self):
         """ Create and connect the netlist """
         self.add_modules()
@@ -48,14 +49,14 @@ class local_bitcell_array(design.design):
         self.add_layout_pins()
 
         self.add_boundary()
-        
+
         self.DRC_LVS()
 
     def add_modules(self):
         """ Add the modules used in this design """
         # This is just used for names
         self.cell = factory.create(module_type="bitcell")
-        
+
         self.bitcell_array = factory.create(module_type="replica_bitcell_array",
                                             cols=self.cols,
                                             rows=self.rows,
@@ -68,7 +69,7 @@ class local_bitcell_array(design.design):
                                        rows=self.rows,
                                        cols=self.cols)
         self.add_mod(self.wl_array)
-        
+
     def create_instances(self):
         """ Create the module instances used in this design """
 
@@ -78,5 +79,3 @@ class local_bitcell_array(design.design):
         self.array_inst = self.add_inst(mod=self.bitcell_array,
                                         offset=self.wl_inst.lr())
         self.connect_inst(self.pins)
-
-        

compiler/modules/replica_bitcell_array.py

@@ -5,14 +5,14 @@
 #
 
 import debug
-import design
+import bitcell_base_array
 from tech import drc, spice, cell_properties
 from vector import vector
 from globals import OPTS
 from sram_factory import factory
 
 
-class replica_bitcell_array(design.design):
+class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
     """
     Creates a bitcell arrow of cols x rows and then adds the replica
     and dummy columns and rows.  Replica columns are on the left and
@@ -22,7 +22,7 @@ class replica_bitcell_array(design.design):
     bitcell (Bl/BR disconnected).
     """
     def __init__(self, rows, cols, left_rbl, right_rbl, bitcell_ports, name, add_replica=True):
-        design.design.__init__(self, name)
+        super().__init__(name, rows, cols, column_offset=0)
         debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
         self.add_comment("rows: {0} cols: {1}".format(rows, cols))
 
@@ -90,9 +90,6 @@ class replica_bitcell_array(design.design):
           1 x (rows + 4)
         """
 
-        # Bitcell for port names only
-        self.cell = factory.create(module_type="bitcell")
-
         # Bitcell array
         self.bitcell_array = factory.create(module_type="bitcell_array",
                                             column_offset=1 + self.add_left_rbl,

compiler/tests/05_local_bitcell_array_test.py

@@ -8,14 +8,14 @@
 #
 import unittest
 from testutils import *
-import sys,os
+import sys, os
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
-from globals import OPTS
 from sram_factory import factory
 import debug
 
-@unittest.skip("SKIPPING 05_local_bitcell_array_test")
+
+#@unittest.skip("SKIPPING 05_local_bitcell_array_test")
 class local_bitcell_array_test(openram_test):
 
     def runTest(self):
@@ -25,9 +25,10 @@ class local_bitcell_array_test(openram_test):
         debug.info(2, "Testing 4x4 local bitcell array for 6t_cell")
         a = factory.create(module_type="local_bitcell_array", cols=4, rows=4)
         self.local_check(a)
-        
+
         globals.end_openram()
 
+
 # run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()