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https://github.com/VLSIDA/OpenRAM.git
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Reabstracting bit and word line names.
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@@ -8,14 +8,14 @@
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#
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import unittest
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from testutils import *
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import sys,os
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import sys, os
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sys.path.append(os.getenv("OPENRAM_HOME"))
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import globals
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from globals import OPTS
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from sram_factory import factory
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import debug
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@unittest.skip("SKIPPING 05_local_bitcell_array_test")
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#@unittest.skip("SKIPPING 05_local_bitcell_array_test")
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class local_bitcell_array_test(openram_test):
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def runTest(self):
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@@ -25,9 +25,10 @@ class local_bitcell_array_test(openram_test):
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debug.info(2, "Testing 4x4 local bitcell array for 6t_cell")
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a = factory.create(module_type="local_bitcell_array", cols=4, rows=4)
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self.local_check(a)
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globals.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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