Reabstracting bit and word line names.

compiler/modules/local_bitcell_array.py

@@ -8,6 +8,7 @@
 import design
 from globals import OPTS
 from sram_factory import factory
+import debug
 
 
 class local_bitcell_array(design.design):
@@ -26,7 +27,7 @@ class local_bitcell_array(design.design):
         self.left_rbl = left_rbl
         self.right_rbl = right_rbl
         self.all_ports = ports
-        
+
         self.create_netlist()
         if not OPTS.netlist_only:
             self.create_layout()
@@ -34,7 +35,7 @@ class local_bitcell_array(design.design):
         # We don't offset this because we need to align
         # the replica bitcell in the control logic
         # self.offset_all_coordinates()
-        
+
     def create_netlist(self):
         """ Create and connect the netlist """
         self.add_modules()
@@ -48,14 +49,14 @@ class local_bitcell_array(design.design):
         self.add_layout_pins()
 
         self.add_boundary()
-        
+
         self.DRC_LVS()
 
     def add_modules(self):
         """ Add the modules used in this design """
         # This is just used for names
         self.cell = factory.create(module_type="bitcell")
-        
+
         self.bitcell_array = factory.create(module_type="replica_bitcell_array",
                                             cols=self.cols,
                                             rows=self.rows,
@@ -68,7 +69,7 @@ class local_bitcell_array(design.design):
                                        rows=self.rows,
                                        cols=self.cols)
         self.add_mod(self.wl_array)
-        
+
     def create_instances(self):
         """ Create the module instances used in this design """
 
@@ -78,5 +79,3 @@ class local_bitcell_array(design.design):
         self.array_inst = self.add_inst(mod=self.bitcell_array,
                                         offset=self.wl_inst.lr())
         self.connect_inst(self.pins)
-
-