Reabstracting bit and word line names.

compiler/modules/bitcell_base_array.py

@@ -8,6 +8,7 @@
 import debug
 import design
 from tech import cell_properties
+from sram_factory import factory
 
 
 class bitcell_base_array(design.design):
@@ -15,7 +16,7 @@ class bitcell_base_array(design.design):
     Abstract base class for bitcell-arrays -- bitcell, dummy, replica
     """
     def __init__(self, name, rows, cols, column_offset):
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
         self.add_comment("rows: {0} cols: {1}".format(rows, cols))
 
@@ -23,41 +24,40 @@ class bitcell_base_array(design.design):
         self.row_size = rows
         self.column_offset = column_offset
 
-    def get_all_bitline_names(self):
+        # Bitcell for port names only
+        self.cell = factory.create(module_type="bitcell")
+        
+        self.create_all_bitline_names()
+        self.create_all_wordline_names()
 
-        res = list()
+    def get_all_bitline_names(self, prefix=""):
+        return [prefix + x for x in self.bitline_names]
+
+    def create_all_bitline_names(self):
+        self.bitline_names = list()
         bitline_names = self.cell.get_all_bitline_names()
 
-        # We have to keep the order of self.pins, otherwise we connect
-        # it wrong in the spice netlist
-        for pin in self.pins:
-            for bl_name in bitline_names:
-                if bl_name in pin:
-                    res.append(pin)
-        return res
+        for col in range(self.column_size):
+            for cell_column in bitline_names:
+                self.bitline_names.append("{0}_{1}".format(cell_column, col))
 
-    def get_all_wordline_names(self):
+    def get_all_wordline_names(self, prefix=""):
+        return [prefix + x for x in self.wordline_names]
 
-        res = list()
+    def create_all_wordline_names(self):
+
+        self.wordline_names = list()
         wordline_names = self.cell.get_all_wl_names()
 
-        # We have to keep the order of self.pins, otherwise we connect
-        # it wrong in the spice netlist
-        for pin in self.pins:
-            for wl_name in wordline_names:
-                if wl_name in pin:
-                    res.append(pin)
-        return res
+        for row in range(self.row_size):
+            for cell_row in wordline_names:
+                self.wordline_names.append("{0}_{1}".format(cell_row, row))
 
     def add_pins(self):
-        row_list = self.cell.get_all_wl_names()
-        column_list = self.cell.get_all_bitline_names()
-        for col in range(self.column_size):
-            for cell_column in column_list:
-                self.add_pin(cell_column+"_{0}".format(col), "INOUT")
-        for row in range(self.row_size):
-            for cell_row in row_list:
-                    self.add_pin(cell_row+"_{0}".format(row), "INPUT")
+        for bl_name in self.bitline_names:
+            self.add_pin(bl_name, "INOUT")
+        for wl_name in self.wordline_names:
+            self.add_pin(wl_name, "INPUT")
         self.add_pin("vdd", "POWER")
         self.add_pin("gnd", "GROUND")
 
@@ -66,13 +66,10 @@ class bitcell_base_array(design.design):
         indexed by column and row, for instance use in bitcell_array """
 
         bitcell_pins = []
-
-        pin_names = self.cell.get_all_bitline_names()
-        for pin in pin_names:
-            bitcell_pins.append(pin + "_{0}".format(col))
-        pin_names = self.cell.get_all_wl_names()
-        for pin in pin_names:
-            bitcell_pins.append(pin + "_{0}".format(row))
+        # bitlines
+        bitcell_pins.extend([x for x in self.bitline_names if x.endswith("_{0}".format(col))])
+        # wordlines
+        bitcell_pins.extend([x for x in self.wordline_names if x.endswith("_{0}".format(row))])
         bitcell_pins.append("vdd")
         bitcell_pins.append("gnd")
 
@@ -81,22 +78,21 @@ class bitcell_base_array(design.design):
     def add_layout_pins(self):
         """ Add the layout pins """
 
-        row_list = self.cell.get_all_wl_names()
-        column_list = self.cell.get_all_bitline_names()
-
+        bitline_names = self.cell.get_all_bitline_names()
         for col in range(self.column_size):
-            for cell_column in column_list:
-                bl_pin = self.cell_inst[0, col].get_pin(cell_column)
-                self.add_layout_pin(text=cell_column + "_{0}".format(col),
+            for bl_name in bitline_names:
+                bl_pin = self.cell_inst[0, col].get_pin(bl_name)
+                self.add_layout_pin(text="{0}_{1}".format(bl_name, col),
                                     layer=bl_pin.layer,
                                     offset=bl_pin.ll().scale(1, 0),
                                     width=bl_pin.width(),
                                     height=self.height)
 
+        wl_names = self.cell.get_all_wl_names()
         for row in range(self.row_size):
-            for cell_row in row_list:
-                wl_pin = self.cell_inst[row, 0].get_pin(cell_row)
-                self.add_layout_pin(text=cell_row + "_{0}".format(row),
+            for wl_name in wl_names:
+                wl_pin = self.cell_inst[row, 0].get_pin(wl_name)
+                self.add_layout_pin(text="{0}_{1}".format(wl_name, row),
                                     layer=wl_pin.layer,
                                     offset=wl_pin.ll().scale(0, 1),
                                     width=self.width,