luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 09:58:33 +02:00
Code Issues Packages Projects Releases Wiki Activity

Reabstracting bit and word line names.

Browse Source
This commit is contained in:
mrg
2020-08-06 11:17:49 -07:00
parent 037de96989
commit eef97ff215
5 changed files with 67 additions and 73 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/bitcell_array.py
+14 -13
View File
@@ -13,9 +13,8 @@ from sram_factory import factory
class bitcell_array(bitcell_base_array):
"""
Creates a rows x cols array of memory cells. Assumes bit-lines
and word line is connected by abutment.
Connects the word lines and bit lines.
Creates a rows x cols array of memory cells.
Assumes bit-lines and word lines are connected by abutment.
"""
def __init__(self, rows, cols, column_offset=0, name=""):
super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
@@ -27,7 +26,7 @@ class bitcell_array(bitcell_base_array):
# We don't offset this because we need to align
# the replica bitcell in the control logic
# self.offset_all_coordinates()
def create_netlist(self):
""" Create and connect the netlist """
self.add_modules()
@@ -41,7 +40,7 @@ class bitcell_array(bitcell_base_array):
self.add_layout_pins()
self.add_boundary()
self.DRC_LVS()
def add_modules(self):
@@ -58,20 +57,20 @@ class bitcell_array(bitcell_base_array):
self.cell_inst[row, col]=self.add_inst(name=name,
mod=self.cell)
self.connect_inst(self.get_bitcell_pins(row, col))
def analytical_power(self, corner, load):
"""Power of Bitcell array and bitline in nW."""
# Dynamic Power from Bitline
bl_wire = self.gen_bl_wire()
cell_load = 2 * bl_wire.return_input_cap()
bl_swing = OPTS.rbl_delay_percentage
freq = spice["default_event_frequency"]
bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
# Calculate the bitcell power which currently only includes leakage
cell_power = self.cell.analytical_power(corner, load)
# Leakage power grows with entire array and bitlines.
total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
cell_power.leakage * self.column_size * self.row_size)
@@ -83,7 +82,8 @@ class bitcell_array(bitcell_base_array):
else:
width = self.width
wl_wire = self.generate_rc_net(int(self.column_size), width, drc("minwidth_m1"))
wl_wire.wire_c = 2 * spice["min_tx_gate_c"] + wl_wire.wire_c # 2 access tx gate per cell
# 2 access tx gate per cell
wl_wire.wire_c = 2 * spice["min_tx_gate_c"] + wl_wire.wire_c
return wl_wire
def gen_bl_wire(self):
@@ -93,7 +93,8 @@ class bitcell_array(bitcell_base_array):
height = self.height
bl_pos = 0
bl_wire = self.generate_rc_net(int(self.row_size - bl_pos), height, drc("minwidth_m1"))
bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
# 1 access tx d/s per cell
bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c
return bl_wire
def get_wordline_cin(self):
@@ -102,7 +103,7 @@ class bitcell_array(bitcell_base_array):
bitcell_wl_cin = self.cell.get_wl_cin()
total_cin = bitcell_wl_cin * self.column_size
return total_cin
def graph_exclude_bits(self, targ_row, targ_col):
"""Excludes bits in column from being added to graph except target"""
# Function is not robust with column mux configurations
@@ -111,7 +112,7 @@ class bitcell_array(bitcell_base_array):
if row == targ_row and col == targ_col:
continue
self.graph_inst_exclude.add(self.cell_inst[row, col])
def get_cell_name(self, inst_name, row, col):
"""Gets the spice name of the target bitcell."""
return inst_name + '.x' + self.cell_inst[row, col].name, self.cell_inst[row, col]