mirror of https://github.com/VLSIDA/OpenRAM.git
skip test file
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@ -25,7 +25,7 @@ class rom():
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word_size=OPTS.word_size,
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word_size=OPTS.word_size,
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words_per_row=OPTS.words_per_row,
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words_per_row=OPTS.words_per_row,
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rom_endian=OPTS.rom_endian,
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rom_endian=OPTS.rom_endian,
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scramble_bits=OPTS.scramble_bits
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scramble_bits=OPTS.scramble_bits,
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strap_spacing=OPTS.strap_spacing)
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strap_spacing=OPTS.strap_spacing)
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if name is None:
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if name is None:
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@ -1,38 +0,0 @@
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#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import unittest
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from testutils import *
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import sys, os
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import openram
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from openram import OPTS
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from openram.sram_factory import factory
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from openram import debug
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class rom_bank_test(openram_test):
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def runTest(self):
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config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
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openram.init_openram(config_file, is_unit_test=True)
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debug.info(1, "Testing 64 byte rom cell")
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test_data = "{0}/{1}/rom_data_64B".format(os.getenv("OPENRAM_HOME"), OPTS.rom_data_dir)
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a = factory.create(module_type="rom_base_bank", strap_spacing = 8, data_file = test_data, word_size = 1)
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self.local_check(a)
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a.sp_write(OPTS.openram_temp + 'simulation_file.sp')
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openram.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = openram.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main(testRunner=debugTestRunner())
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@ -0,0 +1,9 @@
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05_rom_base_bank_1kB_test.py
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05_rom_base_bank_4kB_test.py
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05_rom_array_test.py
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05_rom_decoder_test.py
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05_rom_precharge_array_test.py
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05_rom_wordline_driver_array_test.py
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05_rom_decoder_buffer_array_test.py
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05_rom_column_mux_array_test.py
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05_rom_control_logic_test.py
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