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Errors in contributors.

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Matt Guthaus 2018-11-16 08:26:09 -08:00
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@ -181,7 +181,7 @@ OpenRAM is licensed under the [BSD 3-clause License](./LICENSE).
- [Matthew Guthaus] from [VLSIDA] created the OpenRAM project and is the lead architect. - [Matthew Guthaus] from [VLSIDA] created the OpenRAM project and is the lead architect.
- [James Stine] from [VLSIARCH] co-founded the project. - [James Stine] from [VLSIARCH] co-founded the project.
- Hunter Nichols maintains and updates the timing characterization. - Hunter Nichols maintains and updates the timing characterization.
- Michael Grims created and maintains the multiport netlist code. - Michael Grimes created and maintains the multiport netlist code.
- Jennifer Sowash is creating the OpenRAM IP library. - Jennifer Sowash is creating the OpenRAM IP library.
- Jesse Cirimelli-Low created the datasheet generation. - Jesse Cirimelli-Low created the datasheet generation.
- Samira Ataei created early multi-bank layouts and control logic. - Samira Ataei created early multi-bank layouts and control logic.
@ -190,6 +190,8 @@ OpenRAM is licensed under the [BSD 3-clause License](./LICENSE).
- Brian Chen created early prototypes of the timing characterizer. - Brian Chen created early prototypes of the timing characterizer.
- Jeff Butera created early prototypes of the bank layout. - Jeff Butera created early prototypes of the bank layout.
If I forgot to add you, please let me know!
* * * * * *
[Matthew Guthaus]: https://users.soe.ucsc.edu/~mrg [Matthew Guthaus]: https://users.soe.ucsc.edu/~mrg