Merge branch 's8_update' of github.com:VLSIDA/PrivateRAM into s8_update

compiler/base/hierarchy_layout.py

@@ -17,6 +17,7 @@ import os
 from globals import OPTS
 from vector import vector
 from pin_layout import pin_layout
+from utils import round_to_grid
 
 
 class layout():
@@ -1213,7 +1214,8 @@ class layout():
         else:
             # Hack for min area
             if OPTS.tech_name == "s8":
-                height = width = sqrt(drc["minarea_m3"])
+                width = round_to_grid(sqrt(drc["minarea_m3"]))
+                height = round_to_grid(drc["minarea_m3"]/width)
             else:
                 width = via.width
                 height = via.height

compiler/pgates/single_level_column_mux.py

@@ -7,7 +7,7 @@
 #
 import pgate
 import debug
-from tech import drc
+from tech import drc, layer
 from vector import vector
 from sram_factory import factory
 import logical_effort
@@ -57,7 +57,10 @@ class single_level_column_mux(pgate.pgate):
 
         # Adds nmos_lower,nmos_upper to the module
         self.ptx_width = self.tx_size * drc("minwidth_tx")
-        self.nmos = factory.create(module_type="ptx", width=self.ptx_width)
+        self.nmos = factory.create(module_type="ptx",
+                                    width=self.ptx_width,
+                                    add_source_contact=False,
+                                    add_drain_contact=False)
         self.add_mod(self.nmos)
 
     def add_pins(self):
@@ -66,26 +69,29 @@ class single_level_column_mux(pgate.pgate):
     def add_bitline_pins(self):
         """ Add the top and bottom pins to this cell """
 
-        bl_pos = vector(self.bitcell.get_pin(self.bitcell_bl).lx(), 0)
+        bl_pin=self.bitcell.get_pin(self.bitcell_bl)
-        br_pos = vector(self.bitcell.get_pin(self.bitcell_br).lx(), 0)
+        br_pin=self.bitcell.get_pin(self.bitcell_br)
+
+        bl_pos = vector(bl_pin.lx(), 0)
+        br_pos = vector(br_pin.lx(), 0)
 
         # bl and br
         self.add_layout_pin(text="bl",
-                            layer="m2",
+                            layer=bl_pin.layer,
                             offset=bl_pos + vector(0, self.height - self.pin_height),
                             height=self.pin_height)
         self.add_layout_pin(text="br",
-                            layer="m2",
+                            layer=br_pin.layer,
                             offset=br_pos + vector(0, self.height - self.pin_height),
                             height=self.pin_height)
 
         # bl_out and br_out
         self.add_layout_pin(text="bl_out",
-                            layer="m2",
+                            layer=bl_pin.layer,
                             offset=bl_pos,
                             height=self.pin_height)
         self.add_layout_pin(text="br_out",
-                            layer="m2",
+                            layer=br_pin.layer,
                             offset=br_pos,
                             height=self.pin_height)
 
@@ -102,7 +108,7 @@ class single_level_column_mux(pgate.pgate):
 
         # This aligns it directly above the other tx with gates abutting
         nmos_upper_position = nmos_lower_position \
-                              + vector(0, self.nmos.active_height + self.poly_space)
+                                + vector(0, self.nmos.active_height + self.active_space)
         self.nmos_upper = self.add_inst(name="mux_tx2",
                                         mod=self.nmos,
                                         offset=nmos_upper_position)
@@ -111,11 +117,10 @@ class single_level_column_mux(pgate.pgate):
     def connect_poly(self):
         """ Connect the poly gate of the two pass transistors """
 
-        height = self.nmos_upper.get_pin("G").uy() - self.nmos_lower.get_pin("G").by()
         self.add_layout_pin(text="sel",
                             layer="poly",
-                            offset=self.nmos_lower.get_pin("G").ll(),
+                            offset=self.nmos_lower.get_pin("G").ul() - vector(0,self.poly_extend_active),
-                            height=height)
+                            height=self.active_space)
 
     def connect_bitlines(self):
         """ Connect the bitlines to the mux transistors """
@@ -131,23 +136,53 @@ class single_level_column_mux(pgate.pgate):
         nmos_upper_s_pin = self.nmos_upper.get_pin("S")
         nmos_upper_d_pin = self.nmos_upper.get_pin("D")
 
+        # If li exists, use li and m1 for the mux, otherwise use m1 and m2
+        if "li" in layer:
+            col_mux_stack = self.li_stack
+        else:
+            col_mux_stack = self.m1_stack
+
         # Add vias to bl, br_out, nmos_upper/S, nmos_lower/D
-        self.add_via_center(layers=self.m1_stack,
+        self.add_via_center(layers=col_mux_stack,
                             offset=bl_pin.bc(),
                             directions=("V", "V"))
-        self.add_via_center(layers=self.m1_stack,
+        self.add_via_center(layers=col_mux_stack,
                             offset=br_out_pin.uc(),
                             directions=("V", "V"))
-        self.add_via_center(layers=self.m1_stack,
+        self.add_via_center(layers=col_mux_stack,
                             offset=nmos_upper_s_pin.center(),
                             directions=("V", "V"))
-        self.add_via_center(layers=self.m1_stack,
+        self.add_via_center(layers=col_mux_stack,
                             offset=nmos_lower_d_pin.center(),
                             directions=("V", "V"))
 
+        # Add diffusion contacts
+        # These were previously omitted with the options: add_source_contact=False, add_drain_contact=False
+        # They are added now and not previously due to a s8 tech special case in which the contacts intersected the mux intraconnect
+        self.add_via_center(layers=self.active_stack,
+                            offset=nmos_upper_d_pin.center(),
+                            directions=("V", "V"),
+                            implant_type="n",
+                            well_type="nwell")
+        self.add_via_center(layers=self.active_stack,
+                            offset=nmos_lower_s_pin.center(),
+                            directions=("V", "V"),
+                            implant_type="n",
+                            well_type="nwell")
+        self.add_via_center(layers=self.active_stack,
+                            offset=nmos_upper_s_pin.center(),
+                            directions=("V", "V"),
+                            implant_type="n",
+                            well_type="nwell")
+        self.add_via_center(layers=self.active_stack,
+                            offset=nmos_lower_d_pin.center(),
+                            directions=("V", "V"),
+                            implant_type="n",
+                            well_type="nwell")
+
         # bl -> nmos_upper/D on metal1
         # bl_out -> nmos_upper/S on metal2
-        self.add_path("m1",
+        self.add_path(col_mux_stack[0],
                       [bl_pin.ll(), vector(nmos_upper_d_pin.cx(), bl_pin.by()),
                        nmos_upper_d_pin.center()])
         # halfway up, move over
@@ -155,12 +190,12 @@ class single_level_column_mux(pgate.pgate):
                + nmos_upper_s_pin.bc().scale(0, 0.4)
         mid2 = bl_out_pin.uc().scale(0, 0.4) \
                + nmos_upper_s_pin.bc().scale(1, 0.4)
-        self.add_path("m2",
+        self.add_path(col_mux_stack[2],
-                      [bl_out_pin.uc(), mid1, mid2, nmos_upper_s_pin.bc()])
+                      [bl_out_pin.uc(), mid1, mid2, nmos_upper_s_pin.center()])
 
         # br -> nmos_lower/D on metal2
         # br_out -> nmos_lower/S on metal1
-        self.add_path("m1",
+        self.add_path(col_mux_stack[0],
                       [br_out_pin.uc(),
                        vector(nmos_lower_s_pin.cx(), br_out_pin.uy()),
                        nmos_lower_s_pin.center()])
@@ -169,8 +204,8 @@ class single_level_column_mux(pgate.pgate):
                + nmos_lower_d_pin.uc().scale(0,0.5)
         mid2 = br_pin.bc().scale(0,0.5) \
                + nmos_lower_d_pin.uc().scale(1,0.5)
-        self.add_path("m2",
+        self.add_path(col_mux_stack[2],
-                      [br_pin.bc(), mid1, mid2, nmos_lower_d_pin.uc()])
+                      [br_pin.bc(), mid1, mid2, nmos_lower_d_pin.center()])
 
     def add_wells(self):
         """
@@ -192,10 +227,11 @@ class single_level_column_mux(pgate.pgate):
                            start_layer="m1")
 
         # Add well enclosure over all the tx and contact
-        self.add_rect(layer="pwell",
+        if "pwell" in layer:
-                      offset=vector(0, 0),
+            self.add_rect(layer="pwell",
-                      width=self.bitcell.width,
+                          offset=vector(0, 0),
-                      height=self.height)
+                          width=self.bitcell.width,
+                          height=self.height)
 
     def get_stage_effort(self, corner, slew, load):
         """
@@ -211,4 +247,3 @@ class single_level_column_mux(pgate.pgate):
                                              load,
                                              parasitic_delay,
                                              False)
-

compiler/tests/04_single_level_column_mux_pbitcell_test.py

@@ -0,0 +1,49 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+#@unittest.skip("SKIPPING 04_driver_test")
+
+class single_level_column_mux_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # check single level column mux in multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 1
+
+        factory.reset()
+        debug.info(2, "Checking column mux for pbitcell (innermost connections)")
+        tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
+        self.local_check(tx)
+
+        factory.reset()
+        debug.info(2, "Checking column mux for pbitcell (outermost connections)")
+        tx = factory.create(module_type="single_level_column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2")
+        self.local_check(tx)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/04_single_level_column_mux_test.py

@@ -28,22 +28,6 @@ class single_level_column_mux_test(openram_test):
         tx = factory.create(module_type="single_level_column_mux", tx_size=8)
         self.local_check(tx)
 
-        # check single level column mux in multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_r_ports = 1
-        OPTS.num_w_ports = 1
-
-        factory.reset()
-        debug.info(2, "Checking column mux for pbitcell (innermost connections)")
-        tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
-        self.local_check(tx)
-        
-        factory.reset()
-        debug.info(2, "Checking column mux for pbitcell (outermost connections)")
-        tx = factory.create(module_type="single_level_column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2")
-        self.local_check(tx)
-
         globals.end_openram()
 
 # run the test from the command line

compiler/tests/07_single_level_column_mux_array_pbitcell_test.py

@@ -0,0 +1,55 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class single_level_column_mux_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        import single_level_column_mux_array
+
+        # check single level column mux array in multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 1
+
+        factory.reset()
+        debug.info(1, "Testing sample for 2-way column_mux_array in multi-port")
+        a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0")
+        self.local_check(a)
+
+        debug.info(1, "Testing sample for 4-way column_mux_array  in multi-port")
+        a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
+        self.local_check(a)
+
+        debug.info(1, "Testing sample for 8-way column_mux_array  in multi-port (innermost connections)")
+        a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
+        self.local_check(a)
+
+        debug.info(1, "Testing sample for 8-way column_mux_array  in multi-port (outermost connections)")
+        a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2")
+        self.local_check(a)
+
+        globals.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/07_single_level_column_mux_array_test.py

@@ -34,29 +34,6 @@ class single_level_column_mux_test(openram_test):
         a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4)
         self.local_check(a)
 
-        # check single level column mux array in multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_r_ports = 1
-        OPTS.num_w_ports = 1
-
-        factory.reset()
-        debug.info(1, "Testing sample for 2-way column_mux_array in multi-port")
-        a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0")
-        self.local_check(a)
-
-        debug.info(1, "Testing sample for 4-way column_mux_array  in multi-port")
-        a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
-        self.local_check(a)
-
-        debug.info(1, "Testing sample for 8-way column_mux_array  in multi-port (innermost connections)")
-        a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
-        self.local_check(a)
-        
-        debug.info(1, "Testing sample for 8-way column_mux_array  in multi-port (outermost connections)")
-        a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2")
-        self.local_check(a)
-
         globals.end_openram()
 
 

compiler/tests/08_wordline_driver_pbitcell_test.py

@@ -0,0 +1,44 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+#@unittest.skip("SKIPPING 04_driver_test")
+
+class wordline_driver_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # check wordline driver for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+
+        factory.reset()
+        debug.info(2, "Checking driver (multi-port case)")
+        tx = factory.create(module_type="wordline_driver", rows=8, cols=64)
+        self.local_check(tx)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/08_wordline_driver_test.py

@@ -28,17 +28,6 @@ class wordline_driver_test(openram_test):
         tx = factory.create(module_type="wordline_driver", rows=8, cols=32)
         self.local_check(tx)
 
-        # check wordline driver for multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
-
-        factory.reset()
-        debug.info(2, "Checking driver (multi-port case)")
-        tx = factory.create(module_type="wordline_driver", rows=8, cols=64)
-        self.local_check(tx)
-
         globals.end_openram()
 
 # run the test from the command line

compiler/tests/09_sense_amp_array_test.py

@@ -34,21 +34,6 @@ class sense_amp_test(openram_test):
         a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
         self.local_check(a)
 
-        # check sense amp array for multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
-
-        factory.reset()
-        debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)")
-        a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2)
-        self.local_check(a)
-
-        debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)")
-        a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
-        self.local_check(a)
-
         globals.end_openram()
 
 # run the test from the command line

compiler/tests/09_sense_amp_array_test_pbitcell.py

@@ -0,0 +1,46 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class sense_amp_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        #check sense amp array for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+
+        factory.reset()
+        debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)")
+        a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2)
+        self.local_check(a)
+
+        debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)")
+        a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
+        self.local_check(a)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/10_write_driver_array_pbitcell_test.py

@@ -0,0 +1,46 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class write_driver_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # check write driver array for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+
+        factory.reset()
+        debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)")
+        a = factory.create(module_type="write_driver_array", columns=8, word_size=8)
+        self.local_check(a)
+
+        debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)")
+        a = factory.create(module_type="write_driver_array", columns=16, word_size=8)
+        self.local_check(a)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/10_write_driver_array_test.py

@@ -30,21 +30,6 @@ class write_driver_test(openram_test):
         a = factory.create(module_type="write_driver_array", columns=16, word_size=8)
         self.local_check(a)
 
-        # check write driver array for multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
-
-        factory.reset()
-        debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)")
-        a = factory.create(module_type="write_driver_array", columns=8, word_size=8)
-        self.local_check(a)
-
-        debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)")
-        a = factory.create(module_type="write_driver_array", columns=16, word_size=8)
-        self.local_check(a)
-        
         globals.end_openram()
 
 # run the test from the command line

compiler/tests/10_write_driver_array_wmask_pbitcell_test.py

@@ -0,0 +1,49 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+class write_driver_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # check write driver array for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+
+        factory.reset()
+        debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4 (multi-port case)")
+        a = factory.create(module_type="write_driver_array", columns=8, word_size=8, write_size=4)
+        self.local_check(a)
+
+        debug.info(2, "Testing write_driver_array for columns=16, word_size=8, write_size=4 (multi-port case)")
+        a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4)
+        self.local_check(a)
+
+        globals.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/10_write_driver_array_wmask_test.py

@@ -36,21 +36,6 @@ class write_driver_test(openram_test):
         a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4)
         self.local_check(a)
 
-        # check write driver array for multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
-
-        factory.reset()
-        debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4 (multi-port case)")
-        a = factory.create(module_type="write_driver_array", columns=8, word_size=8, write_size=4)
-        self.local_check(a)
-
-        debug.info(2, "Testing write_driver_array for columns=16, word_size=8, write_size=4 (multi-port case)")
-        a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4)
-        self.local_check(a)
-
         globals.end_openram()
 
 

compiler/tests/10_write_mask_and_array_pbitcell_test.py

@@ -0,0 +1,49 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+class write_mask_and_array_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # check write driver array for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+
+        factory.reset()
+        debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4 (multi-port case)")
+        a = factory.create(module_type="write_mask_and_array", columns=8, word_size=8, write_size=4)
+        self.local_check(a)
+
+        debug.info(2, "Testing write_mask_and_array for columns=16, word_size=8, write_size=2 (multi-port case)")
+        a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2)
+        self.local_check(a)
+
+        globals.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/10_write_mask_and_array_test.py

@@ -36,21 +36,6 @@ class write_mask_and_array_test(openram_test):
         a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2)
         self.local_check(a)
 
-        # check write driver array for multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
-
-        factory.reset()
-        debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4 (multi-port case)")
-        a = factory.create(module_type="write_mask_and_array", columns=8, word_size=8, write_size=4)
-        self.local_check(a)
-
-        debug.info(2, "Testing write_mask_and_array for columns=16, word_size=8, write_size=2 (multi-port case)")
-        a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2)
-        self.local_check(a)
-
         globals.end_openram()
 
 

compiler/tests/19_bank_select_pbitcell_test.py

@@ -0,0 +1,48 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class bank_select_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        OPTS.bitcell = "pbitcell"
+        debug.info(1, "No column mux, rw control logic")
+        a = factory.create(module_type="bank_select", port="rw")
+        self.local_check(a)
+
+        OPTS.num_rw_ports = 0
+        OPTS.num_w_ports = 1
+        OPTS.num_r_ports = 1
+
+        debug.info(1, "No column mux, w control logic")
+        a = factory.create(module_type="bank_select", port="w")
+        self.local_check(a)
+
+        debug.info(1, "No column mux, r control logic")
+        a = factory.create(module_type="bank_select", port="r")
+        self.local_check(a)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/19_bank_select_test.py

@@ -25,23 +25,6 @@ class bank_select_test(openram_test):
         a = factory.create(module_type="bank_select", port="rw")
         self.local_check(a)
 
-        OPTS.bitcell = "pbitcell"
-        debug.info(1, "No column mux, rw control logic")
-        a = factory.create(module_type="bank_select", port="rw")
-        self.local_check(a)
-        
-        OPTS.num_rw_ports = 0
-        OPTS.num_w_ports = 1
-        OPTS.num_r_ports = 1
-
-        debug.info(1, "No column mux, w control logic")
-        a = factory.create(module_type="bank_select", port="w")
-        self.local_check(a)
-        
-        debug.info(1, "No column mux, r control logic")
-        a = factory.create(module_type="bank_select", port="r")
-        self.local_check(a)
-        
         globals.end_openram()
 
 # run the test from the command line