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OpenRAM
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev

This commit is contained in:
mrg 2020-06-25 08:57:37 -07:00
parent da900b89ba 5941e01b51
commit ee0a003298
4 changed files with 22 additions and 12 deletions
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2
compiler/options.py
View File

@ -58,7 +58,7 @@ class options(optparse.Values):
delay_chain_stages = 9 delay_chain_stages = 9
delay_chain_fanout_per_stage = 4 delay_chain_fanout_per_stage = 4
accuracy_requirement = 0.75
################### ###################
# Debug options. # Debug options.

6
compiler/pgates/pgate.py
View File

@ -15,7 +15,7 @@ from vector import vector
from globals import OPTS from globals import OPTS
if(OPTS.tech_name == "sky130"): if(OPTS.tech_name == "sky130"):
from tech import nmos_bins, pmos_bins, accuracy_requirement from tech import nmos_bins, pmos_bins
class pgate(design.design): class pgate(design.design):
@ -400,7 +400,7 @@ class pgate(design.design):
select = -1 select = -1
for i in reversed(range(0, len(scaled_bins))): for i in reversed(range(0, len(scaled_bins))):
if abs(target_width - scaled_bins[i])/target_width <= 1-accuracy_requirement: if abs(target_width - scaled_bins[i])/target_width <= 1-OPTS.accuracy_requirement:
select = i select = i
break break
if select == -1: if select == -1:
@ -434,4 +434,4 @@ class pgate(design.design):
return(scaled_bins) return(scaled_bins)
def bin_accuracy(self, ideal_width, width): def bin_accuracy(self, ideal_width, width):
return abs(1-(ideal_width - width)/ideal_width) return 1-abs((ideal_width - width)/ideal_width)

24
compiler/pgates/pinv.py
View File

@ -20,7 +20,7 @@ from sram_factory import factory
from errors import drc_error from errors import drc_error
if(OPTS.tech_name == "sky130"): if(OPTS.tech_name == "sky130"):
from tech import nmos_bins, pmos_bins, accuracy_requirement from tech import nmos_bins, pmos_bins
class pinv(pgate.pgate): class pinv(pgate.pgate):
@ -31,6 +31,9 @@ class pinv(pgate.pgate):
height is usually the same as the 6t library cell and is measured height is usually the same as the 6t library cell and is measured
from center of rail to rail. from center of rail to rail.
""" """
# binning %error tracker
bin_count = 0
bin_error = 0
def __init__(self, name, size=1, beta=parameter["beta"], height=None, add_wells=True): def __init__(self, name, size=1, beta=parameter["beta"], height=None, add_wells=True):
@ -44,7 +47,7 @@ class pinv(pgate.pgate):
self.nmos_size = size self.nmos_size = size
self.pmos_size = beta * size self.pmos_size = beta * size
self.beta = beta self.beta = beta
pgate.pgate.__init__(self, name, height, add_wells) pgate.pgate.__init__(self, name, height, add_wells)
def create_netlist(self): def create_netlist(self):
@ -166,30 +169,37 @@ class pinv(pgate.pgate):
valid_pmos = [] valid_pmos = []
for bin in pmos_bins: for bin in pmos_bins:
if self.bin_accuracy(self.pmos_width, bin[0]) > accuracy_requirement: if abs(self.bin_accuracy(self.pmos_width, bin[0])) > OPTS.accuracy_requirement and abs(self.bin_accuracy(self.pmos_width, bin[0])) <= 1:
valid_pmos.append(bin) valid_pmos.append(bin)
valid_pmos.sort(key = operator.itemgetter(1)) valid_pmos.sort(key = operator.itemgetter(1))
valid_nmos = [] valid_nmos = []
for bin in nmos_bins: for bin in nmos_bins:
if self.bin_accuracy(self.nmos_width, bin[0]) > accuracy_requirement: if abs(self.bin_accuracy(self.nmos_width, bin[0])) > OPTS.accuracy_requirement and abs(self.bin_accuracy(self.nmos_width, bin[0])) <= 1:
valid_nmos.append(bin) valid_nmos.append(bin)
valid_nmos.sort(key = operator.itemgetter(1)) valid_nmos.sort(key = operator.itemgetter(1))
for bin in valid_pmos: for bin in valid_pmos:
if bin[0]/bin[1] < pmos_height_available: if bin[0]/bin[1] < pmos_height_available:
self.pmos_width = bin[0]/bin[1] self.pmos_width = bin[0]/bin[1]
pmos_mults = valid_pmos[0][1] pmos_mults = bin[1]
break break
for bin in valid_nmos: for bin in valid_nmos:
if bin[0]/bin[1] < nmos_height_available: if bin[0]/bin[1] < nmos_height_available:
self.nmos_width = bin[0]/bin[1] self.nmos_width = bin[0]/bin[1]
nmos_mults = valid_pmos[0][1] nmos_mults = bin[1]
break break
self.tx_mults = max(pmos_mults, nmos_mults) self.tx_mults = max(pmos_mults, nmos_mults)
debug.info(2, "prebinning {0} tx, target: {4}, found {1} x {2} = {3}".format("pmos", self.pmos_width, pmos_mults, self.pmos_width * pmos_mults, self.pmos_size * drc("minwidth_tx")))
debug.info(2, "prebinning {0} tx, target: {4}, found {1} x {2} = {3}".format("nmos", self.nmos_width, nmos_mults, self.nmos_width * nmos_mults, self.nmos_size * drc("minwidth_tx")))
pinv.bin_count += 1
pinv.bin_error += abs(((self.pmos_width * pmos_mults) - (self.pmos_size * drc("minwidth_tx")))/(self.pmos_size * drc("minwidth_tx")))
pinv.bin_count += 1
pinv.bin_error += abs(((self.nmos_width * nmos_mults) - (self.nmos_size * drc("minwidth_tx")))/(self.nmos_size * drc("minwidth_tx")))
debug.info(2, "pinv bin count: {0} pinv bin error: {1} percent error {2}".format(pinv.bin_count, pinv.bin_error, pinv.bin_error/pinv.bin_count))
def add_ptx(self): def add_ptx(self):
""" Create the PMOS and NMOS transistors. """ """ Create the PMOS and NMOS transistors. """
self.nmos = factory.create(module_type="ptx", self.nmos = factory.create(module_type="ptx",

2
compiler/pgates/pinv_dec.py
View File

@ -14,7 +14,7 @@ from globals import OPTS
from sram_factory import factory from sram_factory import factory
if(OPTS.tech_name == "sky130"): if(OPTS.tech_name == "sky130"):
from tech import nmos_bins, pmos_bins, accuracy_requirement from tech import nmos_bins, pmos_bins
class pinv_dec(pinv.pinv): class pinv_dec(pinv.pinv):