mirror of https://github.com/VLSIDA/OpenRAM.git
Added some data variation checking
This commit is contained in:
Hunter Nichols
parent
d527b7da62
commit
ee03b4ecb8
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@ -112,6 +112,7 @@ class control_logic(design.design):
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c = reload(__import__(OPTS.replica_bitline))
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replica_bitline = getattr(c, OPTS.replica_bitline)
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bitcell_loads = int(math.ceil(self.num_rows * parameter["rbl_height_percentage"]))
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#Use a model to determine the delays with that heuristic
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if OPTS.use_tech_delay_chain_size: #Use tech parameters if set.
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delay_stages = parameter["static_delay_stages"]
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delay_fanout = parameter["static_fanout_per_stage"]
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@ -119,6 +120,8 @@ class control_logic(design.design):
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self.replica_bitline = replica_bitline([delay_fanout]*delay_stages,
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bitcell_loads,
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name="replica_bitline_"+self.port_type)
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if self.sram != None: #Calculate model value even for specified sizes
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self.set_sen_wl_delays()
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else: #Otherwise, use a heuristic and/or model based sizing.
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#First use a heuristic
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@ -126,13 +129,10 @@ class control_logic(design.design):
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self.replica_bitline = replica_bitline([delay_fanout_heuristic]*delay_stages_heuristic,
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bitcell_loads,
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name="replica_bitline_"+self.port_type)
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#Use a model to determine the delays with that heuristic
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if self.sram != None:
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if self.sram != None: #Calculate delays for potential re-sizing
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self.set_sen_wl_delays()
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#Resize if necessary
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if self.sram != None and self.enable_delay_chain_resizing and not self.does_sen_total_timing_match(): #check condition based on resizing method
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#Resize if necessary, condition depends on resizing method
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if self.sram != None and self.enable_delay_chain_resizing and not self.does_sen_total_timing_match():
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#This resizes to match fall and rise delays, can make the delay chain weird sizes.
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# stage_list = self.get_dynamic_delay_fanout_list(delay_stages_heuristic, delay_fanout_heuristic)
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# self.replica_bitline = replica_bitline(stage_list,
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@ -2,7 +2,7 @@ word_size = 1
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num_words = 16
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tech_name = "freepdk45"
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process_corners = ["TT", "FF"]
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process_corners = ["TT", "FF", "SS", "SF", "FS"]
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supply_voltages = [1.0]
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temperatures = [25]
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@ -2,31 +2,35 @@
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"""
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Run a regression test on various srams
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"""
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import csv,sys,os
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import pandas as pd
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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import csv
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from sram import sram
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from sram_config import sram_config
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import pandas as pd
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MODEL_DIR = "model_data/"
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class data_collection(openram_test):
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def runTest(self):
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self.init_data_gen()
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word_size, num_words, words_per_row = 4, 16, 1
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#Get data and write to CSV
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self.init_data_gen()
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self.set_delay_chain(2,3)
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self.save_data_sram_corners(word_size, num_words, words_per_row)
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wl_dataframe, sae_dataframe = self.get_csv_data()
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self.evaluate_data(wl_dataframe, sae_dataframe)
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#Only care about the measured data for now, select from all file names. Names are defined in model_check
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#Run again but with different delay chain sizes
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self.init_data_gen()
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self.set_delay_chain(4,2)
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self.save_data_sram_corners(word_size, num_words, words_per_row)
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wl_dataframe, sae_dataframe = self.get_csv_data()
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self.evaluate_data(wl_dataframe, sae_dataframe)
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@ -43,7 +47,9 @@ class data_collection(openram_test):
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def evaluate_data(self, wl_dataframe, sae_dataframe):
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"""Analyze the delay error and variation error"""
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delay_error = self.calculate_delay_error(wl_dataframe, sae_dataframe)
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debug.info(1, "Delay errors:\n{}".format(delay_error))
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debug.info(1, "Delay errors:{}".format(delay_error))
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variation_error = self.calculate_delay_variation_error(wl_dataframe, sae_dataframe)
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debug.info(1, "Variation errors:{}".format(variation_error))
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def calculate_delay_error(self, wl_dataframe, sae_dataframe):
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"""Calculates the percentage difference in delays between the wordline and sense amp enable"""
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@ -51,14 +57,36 @@ class data_collection(openram_test):
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error_list = []
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row_count = 0
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for wl_row, sae_row in zip(wl_dataframe.itertuples(), sae_dataframe.itertuples()):
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debug.info(1, "wl_row:\n{}".format(wl_row))
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debug.info(2, "wl_row:{}".format(wl_row))
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wl_sum = sum(wl_row[start_data_pos+1:])
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debug.info(1, "wl_sum:\n{}".format(wl_sum))
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debug.info(2, "wl_sum:{}".format(wl_sum))
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sae_sum = sum(sae_row[start_data_pos+1:])
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error_list.append(abs((wl_sum-sae_sum)/wl_sum))
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return error_list
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def calculate_delay_variation_error(self, wl_dataframe, sae_dataframe):
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"""Measures a base delay from the first corner then the variations from that base"""
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start_data_pos = len(self.config_fields)
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variation_error_list = []
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count = 0
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for wl_row, sae_row in zip(wl_dataframe.itertuples(), sae_dataframe.itertuples()):
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if count == 0:
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#Create a base delay, variation is defined as the difference between this base
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wl_base = sum(wl_row[start_data_pos+1:])
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debug.info(1, "wl_sum base:{}".format(wl_base))
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sae_base = sum(sae_row[start_data_pos+1:])
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variation_error_list.append(0.0)
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else:
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#Calculate the variation from the respective base and then difference between the variations
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wl_sum = sum(wl_row[start_data_pos+1:])
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wl_base_diff = abs((wl_base-wl_sum)/wl_base)
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sae_sum = sum(sae_row[start_data_pos+1:])
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sae_base_diff = abs((sae_base-sae_sum)/sae_base)
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variation_diff = abs((wl_base_diff-sae_base_diff)/wl_base_diff)
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variation_error_list.append(variation_diff)
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count+=1
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return variation_error_list
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def save_data_sram_corners(self, word_size, num_words, words_per_row):
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"""Performs corner analysis on a single SRAM configuration"""
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self.create_sram(word_size, num_words, words_per_row)
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@ -80,17 +108,25 @@ class data_collection(openram_test):
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def init_data_gen(self):
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"""Initialization for the data test to run"""
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globals.init_openram("config_data")
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from tech import parameter
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global parameter
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if OPTS.tech_name == "scmos":
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debug.warning("Device models not up to date with scn4m technology.")
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OPTS.spice_name="hspice" #Much faster than ngspice.
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OPTS.trim_netlist = False
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OPTS.netlist_only = True
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OPTS.analytical_delay = False
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OPTS.use_tech_delay_chain_size = True
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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import characterizer
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reload(characterizer)
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def set_delay_chain(self, stages, fanout):
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"""Force change the parameter in the tech file to specify a delay chain configuration"""
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parameter["static_delay_stages"] = stages
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parameter["static_fanout_per_stage"] = fanout
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def close_files(self):
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"""Closes all files stored in the file dict"""
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for key,file in self.csv_files.items():
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@ -133,10 +169,12 @@ class data_collection(openram_test):
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self.csv_writers = {}
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self.file_names = []
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for data_name, header_list in header_dict.items():
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file_name = '{}data_{}b_{}word_{}way_{}.csv'.format(MODEL_DIR,
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file_name = '{}data_{}b_{}word_{}way_dc{}x{}_{}.csv'.format(MODEL_DIR,
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word_size,
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num_words,
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words_per_row,
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parameter["static_delay_stages"],
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parameter["static_fanout_per_stage"],
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data_name)
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self.file_names.append(file_name)
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self.csv_files[data_name] = open(file_name, 'w')
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@ -1,3 +1,6 @@
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.zb_int,Xsram.s_en0
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4,16,1,TT,1.0,25,0.021103999999999998,0.0061908,0.018439,0.017329999999999998,0.0094258,0.018392000000000002,0.011755000000000002
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4,16,1,FF,1.0,25,0.019583,0.005128,0.017439,0.015281,0.008443599999999999,0.017213000000000003,0.010389
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4,16,1,SS,1.0,25,0.022932,0.0074386999999999995,0.019891000000000002,0.019466,0.010501,0.019849,0.013432
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4,16,1,SF,1.0,25,0.019301,0.007507700000000001,0.016878999999999998,0.018834,0.010293,0.017156,0.01299
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4,16,1,FS,1.0,25,0.023601,0.0045925,0.020515,0.015586,0.0085521,0.019967,0.010449
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@ -1,3 +1,6 @@
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.zb_int,Xsram.s_en0
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4,16,1,TT,1.0,25,8.8,2.65,6.4,7.4,4.4,6.4,2.99375
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4,16,1,FF,1.0,25,8.8,2.65,6.4,7.4,4.4,6.4,2.99375
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4,16,1,SS,1.0,25,8.8,2.65,6.4,7.4,4.4,6.4,2.99375
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4,16,1,SF,1.0,25,8.8,2.65,6.4,7.4,4.4,6.4,2.99375
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4,16,1,FS,1.0,25,8.8,2.65,6.4,7.4,4.4,6.4,2.99375
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@ -1,3 +1,6 @@
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.zb_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15
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4,16,1,TT,1.0,25,0.018438,0.0092547,0.013922,0.008679300000000001
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4,16,1,FF,1.0,25,0.017261,0.008002500000000001,0.012757,0.0077545
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4,16,1,SS,1.0,25,0.019962,0.010683,0.015394,0.009734999999999999
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4,16,1,SF,1.0,25,0.017044,0.010483999999999999,0.012825,0.0094333
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4,16,1,FS,1.0,25,0.020398,0.0078018,0.015243999999999999,0.0079892
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@ -1,3 +1,6 @@
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.zb_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15
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4,16,1,TT,1.0,25,4.4,12.4,5.8,5.4
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4,16,1,FF,1.0,25,4.4,12.4,5.8,5.4
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4,16,1,SS,1.0,25,4.4,12.4,5.8,5.4
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4,16,1,SF,1.0,25,4.4,12.4,5.8,5.4
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4,16,1,FS,1.0,25,4.4,12.4,5.8,5.4
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@ -0,0 +1,6 @@
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_2,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_3,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.zb_int,Xsram.s_en0
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4,16,1,TT,1.0,25,0.021141999999999998,0.006257400000000001,0.015622,0.014144,0.017741,0.013434,0.009287,0.018439999999999998,0.011276
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4,16,1,FF,1.0,25,0.019646,0.0052736,0.014601,0.012589,0.016537,0.011916999999999999,0.0083483,0.017246,0.0099574
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4,16,1,SS,1.0,25,0.022917,0.0074182,0.016901,0.015895,0.019267,0.015147,0.010306000000000001,0.01986,0.012834
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4,16,1,SF,1.0,25,0.019208,0.007500799999999999,0.014421999999999999,0.015359999999999999,0.016408,0.014695999999999999,0.010128,0.017086999999999998,0.012516000000000001
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4,16,1,FS,1.0,25,0.023644000000000002,0.0046118,0.017239,0.01283,0.019428,0.012081999999999999,0.0085141,0.020073,0.009944
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@ -0,0 +1,6 @@
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_2,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_3,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.zb_int,Xsram.s_en0
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4,16,1,TT,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,4.4,6.4,2.99375
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4,16,1,FF,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,4.4,6.4,2.99375
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4,16,1,SS,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,4.4,6.4,2.99375
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4,16,1,SF,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,4.4,6.4,2.99375
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4,16,1,FS,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,4.4,6.4,2.99375
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@ -0,0 +1,6 @@
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.zb_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15
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4,16,1,TT,1.0,25,0.018481,0.0093054,0.013848,0.008683999999999999
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4,16,1,FF,1.0,25,0.017331,0.0080465,0.012700999999999999,0.0077613000000000005
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4,16,1,SS,1.0,25,0.019895,0.010660000000000001,0.015356999999999999,0.009745
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4,16,1,SF,1.0,25,0.016984000000000003,0.010501,0.012796,0.009405700000000001
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4,16,1,FS,1.0,25,0.020445,0.007772300000000001,0.015284,0.0079428
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@ -0,0 +1,6 @@
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.zb_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15
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4,16,1,TT,1.0,25,4.4,12.4,5.8,5.4
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4,16,1,FF,1.0,25,4.4,12.4,5.8,5.4
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4,16,1,SS,1.0,25,4.4,12.4,5.8,5.4
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4,16,1,SF,1.0,25,4.4,12.4,5.8,5.4
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4,16,1,FS,1.0,25,4.4,12.4,5.8,5.4
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