Added some data variation checking

compiler/modules/control_logic.py

@@ -112,6 +112,7 @@ class control_logic(design.design):
             c = reload(__import__(OPTS.replica_bitline))
             replica_bitline = getattr(c, OPTS.replica_bitline)
             bitcell_loads = int(math.ceil(self.num_rows * parameter["rbl_height_percentage"]))
+            #Use a model to determine the delays with that heuristic
             if OPTS.use_tech_delay_chain_size: #Use tech parameters if set.
                 delay_stages =  parameter["static_delay_stages"]
                 delay_fanout = parameter["static_fanout_per_stage"]
@@ -119,6 +120,8 @@ class control_logic(design.design):
                 self.replica_bitline = replica_bitline([delay_fanout]*delay_stages,
                                                         bitcell_loads, 
                                                         name="replica_bitline_"+self.port_type)
+                if self.sram != None: #Calculate model value even for specified sizes
+                    self.set_sen_wl_delays()
                 
             else: #Otherwise, use a heuristic and/or model based sizing.
                 #First use a heuristic
@@ -126,13 +129,10 @@ class control_logic(design.design):
                 self.replica_bitline = replica_bitline([delay_fanout_heuristic]*delay_stages_heuristic, 
                                                         bitcell_loads,
                                                         name="replica_bitline_"+self.port_type)
-                
+                if self.sram != None: #Calculate delays for potential re-sizing
-                #Use a model to determine the delays with that heuristic
-                if self.sram != None:
                     self.set_sen_wl_delays()
-               
+                #Resize if necessary, condition depends on resizing method
-                #Resize if necessary
+                if self.sram != None and self.enable_delay_chain_resizing and not self.does_sen_total_timing_match(): 
-                if self.sram != None and self.enable_delay_chain_resizing and not self.does_sen_total_timing_match(): #check condition based on resizing method
                     #This resizes to match fall and rise delays, can make the delay chain weird sizes.
                     # stage_list = self.get_dynamic_delay_fanout_list(delay_stages_heuristic, delay_fanout_heuristic)
                     # self.replica_bitline = replica_bitline(stage_list, 

compiler/tests/config_data.py

@@ -2,7 +2,7 @@ word_size = 1
 num_words = 16
 
 tech_name = "freepdk45"
-process_corners = ["TT", "FF"]
+process_corners = ["TT", "FF", "SS", "SF", "FS"]
 supply_voltages = [1.0]
 temperatures = [25]
 

compiler/tests/delay_data_collection.py

@@ -2,31 +2,35 @@
 """
 Run a regression test on various srams
 """
+import csv,sys,os
+import pandas as pd
 
 import unittest
 from testutils import header,openram_test
-import sys,os
 sys.path.append(os.path.join(sys.path[0],".."))
 import globals
 from globals import OPTS
 import debug
-import csv
 from sram import sram
 from sram_config import sram_config
-import pandas as pd
 
 MODEL_DIR = "model_data/"
 
 class data_collection(openram_test):
 
     def runTest(self):
-        self.init_data_gen()
-     
-        word_size, num_words, words_per_row = 4, 16, 1 
-        #Get data and write to CSV
-        self.save_data_sram_corners(word_size, num_words, words_per_row)
         
-        #Only care about the measured data for now, select from all file names. Names are defined in model_check
+        word_size, num_words, words_per_row = 4, 16, 1 
+        self.init_data_gen()
+        self.set_delay_chain(2,3)
+        self.save_data_sram_corners(word_size, num_words, words_per_row)
+        wl_dataframe, sae_dataframe = self.get_csv_data()
+        self.evaluate_data(wl_dataframe, sae_dataframe)
+        
+        #Run again but with different delay chain sizes
+        self.init_data_gen() 
+        self.set_delay_chain(4,2)
+        self.save_data_sram_corners(word_size, num_words, words_per_row)
         wl_dataframe, sae_dataframe = self.get_csv_data()
         self.evaluate_data(wl_dataframe, sae_dataframe)
         
@@ -43,7 +47,9 @@ class data_collection(openram_test):
     def evaluate_data(self, wl_dataframe, sae_dataframe):
         """Analyze the delay error and variation error"""
         delay_error = self.calculate_delay_error(wl_dataframe, sae_dataframe)
-        debug.info(1, "Delay errors:\n{}".format(delay_error))
+        debug.info(1, "Delay errors:{}".format(delay_error))
+        variation_error = self.calculate_delay_variation_error(wl_dataframe, sae_dataframe)
+        debug.info(1, "Variation errors:{}".format(variation_error))
         
     def calculate_delay_error(self, wl_dataframe, sae_dataframe):
         """Calculates the percentage difference in delays between the wordline and sense amp enable"""
@@ -51,14 +57,36 @@ class data_collection(openram_test):
         error_list = []
         row_count = 0
         for wl_row, sae_row in zip(wl_dataframe.itertuples(), sae_dataframe.itertuples()):             
-            debug.info(1, "wl_row:\n{}".format(wl_row))
+            debug.info(2, "wl_row:{}".format(wl_row))
             wl_sum = sum(wl_row[start_data_pos+1:])
-            debug.info(1, "wl_sum:\n{}".format(wl_sum))
+            debug.info(2, "wl_sum:{}".format(wl_sum))
             sae_sum = sum(sae_row[start_data_pos+1:])
             error_list.append(abs((wl_sum-sae_sum)/wl_sum))
-            
         return error_list
         
+    def calculate_delay_variation_error(self, wl_dataframe, sae_dataframe):
+        """Measures a base delay from the first corner then the variations from that base"""
+        start_data_pos = len(self.config_fields)
+        variation_error_list = []
+        count = 0
+        for wl_row, sae_row in zip(wl_dataframe.itertuples(), sae_dataframe.itertuples()):
+            if count == 0:
+                #Create a base delay, variation is defined as the difference between this base
+                wl_base = sum(wl_row[start_data_pos+1:])
+                debug.info(1, "wl_sum base:{}".format(wl_base))
+                sae_base = sum(sae_row[start_data_pos+1:])
+                variation_error_list.append(0.0)
+            else:
+                #Calculate the variation from the respective base and then difference between the variations
+                wl_sum = sum(wl_row[start_data_pos+1:])
+                wl_base_diff = abs((wl_base-wl_sum)/wl_base)
+                sae_sum = sum(sae_row[start_data_pos+1:])
+                sae_base_diff = abs((sae_base-sae_sum)/sae_base)
+                variation_diff = abs((wl_base_diff-sae_base_diff)/wl_base_diff)
+                variation_error_list.append(variation_diff)
+            count+=1
+        return variation_error_list
+        
     def save_data_sram_corners(self, word_size, num_words, words_per_row):
         """Performs corner analysis on a single SRAM configuration"""
         self.create_sram(word_size, num_words, words_per_row)
@@ -80,17 +108,25 @@ class data_collection(openram_test):
     def init_data_gen(self):
         """Initialization for the data test to run"""
         globals.init_openram("config_data")
+        from tech import parameter
+        global parameter
         if OPTS.tech_name == "scmos":
             debug.warning("Device models not up to date with scn4m technology.")
         OPTS.spice_name="hspice" #Much faster than ngspice.
         OPTS.trim_netlist = False
         OPTS.netlist_only = True
         OPTS.analytical_delay = False
+        OPTS.use_tech_delay_chain_size = True
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
         import characterizer
         reload(characterizer) 
 
+    def set_delay_chain(self, stages, fanout):
+        """Force change the parameter in the tech file to specify a delay chain configuration"""
+        parameter["static_delay_stages"] = stages
+        parameter["static_fanout_per_stage"] = fanout
+        
     def close_files(self):
         """Closes all files stored in the file dict"""
         for key,file in self.csv_files.items():
@@ -133,10 +169,12 @@ class data_collection(openram_test):
         self.csv_writers = {}
         self.file_names = []
         for data_name, header_list in header_dict.items():
-            file_name = '{}data_{}b_{}word_{}way_{}.csv'.format(MODEL_DIR,
+            file_name = '{}data_{}b_{}word_{}way_dc{}x{}_{}.csv'.format(MODEL_DIR,
                                                                 word_size, 
                                                                 num_words, 
-                                                                words_per_row, 
+                                                                words_per_row,
+                                                                parameter["static_delay_stages"],
+                                                                parameter["static_fanout_per_stage"],
                                                                 data_name)
             self.file_names.append(file_name)
             self.csv_files[data_name] = open(file_name, 'w')

compiler/tests/model_data/data_4b_16word_1way_dc2x3_sae_measures.csv

@@ -1,3 +1,6 @@
 word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.zb_int,Xsram.s_en0
 4,16,1,TT,1.0,25,0.021103999999999998,0.0061908,0.018439,0.017329999999999998,0.0094258,0.018392000000000002,0.011755000000000002
 4,16,1,FF,1.0,25,0.019583,0.005128,0.017439,0.015281,0.008443599999999999,0.017213000000000003,0.010389
+4,16,1,SS,1.0,25,0.022932,0.0074386999999999995,0.019891000000000002,0.019466,0.010501,0.019849,0.013432
+4,16,1,SF,1.0,25,0.019301,0.007507700000000001,0.016878999999999998,0.018834,0.010293,0.017156,0.01299
+4,16,1,FS,1.0,25,0.023601,0.0045925,0.020515,0.015586,0.0085521,0.019967,0.010449

compiler/tests/model_data/data_4b_16word_1way_dc2x3_sae_model.csv

@@ -1,3 +1,6 @@
 word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.zb_int,Xsram.s_en0
 4,16,1,TT,1.0,25,8.8,2.65,6.4,7.4,4.4,6.4,2.99375
 4,16,1,FF,1.0,25,8.8,2.65,6.4,7.4,4.4,6.4,2.99375
+4,16,1,SS,1.0,25,8.8,2.65,6.4,7.4,4.4,6.4,2.99375
+4,16,1,SF,1.0,25,8.8,2.65,6.4,7.4,4.4,6.4,2.99375
+4,16,1,FS,1.0,25,8.8,2.65,6.4,7.4,4.4,6.4,2.99375

compiler/tests/model_data/data_4b_16word_1way_dc2x3_wl_measures.csv

@@ -1,3 +1,6 @@
 word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.zb_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15
 4,16,1,TT,1.0,25,0.018438,0.0092547,0.013922,0.008679300000000001
 4,16,1,FF,1.0,25,0.017261,0.008002500000000001,0.012757,0.0077545
+4,16,1,SS,1.0,25,0.019962,0.010683,0.015394,0.009734999999999999
+4,16,1,SF,1.0,25,0.017044,0.010483999999999999,0.012825,0.0094333
+4,16,1,FS,1.0,25,0.020398,0.0078018,0.015243999999999999,0.0079892

compiler/tests/model_data/data_4b_16word_1way_dc2x3_wl_model.csv

@@ -1,3 +1,6 @@
 word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.zb_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15
 4,16,1,TT,1.0,25,4.4,12.4,5.8,5.4
 4,16,1,FF,1.0,25,4.4,12.4,5.8,5.4
+4,16,1,SS,1.0,25,4.4,12.4,5.8,5.4
+4,16,1,SF,1.0,25,4.4,12.4,5.8,5.4
+4,16,1,FS,1.0,25,4.4,12.4,5.8,5.4

compiler/tests/model_data/data_4b_16word_1way_dc4x2_sae_measures.csv

@@ -0,0 +1,6 @@
+word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_2,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_3,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.zb_int,Xsram.s_en0
+4,16,1,TT,1.0,25,0.021141999999999998,0.006257400000000001,0.015622,0.014144,0.017741,0.013434,0.009287,0.018439999999999998,0.011276
+4,16,1,FF,1.0,25,0.019646,0.0052736,0.014601,0.012589,0.016537,0.011916999999999999,0.0083483,0.017246,0.0099574
+4,16,1,SS,1.0,25,0.022917,0.0074182,0.016901,0.015895,0.019267,0.015147,0.010306000000000001,0.01986,0.012834
+4,16,1,SF,1.0,25,0.019208,0.007500799999999999,0.014421999999999999,0.015359999999999999,0.016408,0.014695999999999999,0.010128,0.017086999999999998,0.012516000000000001
+4,16,1,FS,1.0,25,0.023644000000000002,0.0046118,0.017239,0.01283,0.019428,0.012081999999999999,0.0085141,0.020073,0.009944

compiler/tests/model_data/data_4b_16word_1way_dc4x2_sae_model.csv

@@ -0,0 +1,6 @@
+word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_2,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_3,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.zb_int,Xsram.s_en0
+4,16,1,TT,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,4.4,6.4,2.99375
+4,16,1,FF,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,4.4,6.4,2.99375
+4,16,1,SS,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,4.4,6.4,2.99375
+4,16,1,SF,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,4.4,6.4,2.99375
+4,16,1,FS,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,4.4,6.4,2.99375

compiler/tests/model_data/data_4b_16word_1way_dc4x2_wl_measures.csv

@@ -0,0 +1,6 @@
+word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.zb_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15
+4,16,1,TT,1.0,25,0.018481,0.0093054,0.013848,0.008683999999999999
+4,16,1,FF,1.0,25,0.017331,0.0080465,0.012700999999999999,0.0077613000000000005
+4,16,1,SS,1.0,25,0.019895,0.010660000000000001,0.015356999999999999,0.009745
+4,16,1,SF,1.0,25,0.016984000000000003,0.010501,0.012796,0.009405700000000001
+4,16,1,FS,1.0,25,0.020445,0.007772300000000001,0.015284,0.0079428

compiler/tests/model_data/data_4b_16word_1way_dc4x2_wl_model.csv

@@ -0,0 +1,6 @@
+word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.zb_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15
+4,16,1,TT,1.0,25,4.4,12.4,5.8,5.4
+4,16,1,FF,1.0,25,4.4,12.4,5.8,5.4
+4,16,1,SS,1.0,25,4.4,12.4,5.8,5.4
+4,16,1,SF,1.0,25,4.4,12.4,5.8,5.4
+4,16,1,FS,1.0,25,4.4,12.4,5.8,5.4