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https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-30 18:02:23 +02:00
Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array.
This commit is contained in:
Matt Guthaus
+117
-121
@@ -34,7 +34,7 @@ class delay_chain(design.design):
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self.add_pins()
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self.create_module()
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self.route_inv()
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self.route_inverters()
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self.add_layout_pins()
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self.DRC_LVS()
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@@ -48,82 +48,69 @@ class delay_chain(design.design):
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def create_module(self):
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""" Add the inverter logical module """
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self.create_inv_list()
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self.inv = pinv(route_output=False)
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self.add_mod(self.inv)
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# half chain length is the width of the layout
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# invs are stacked into 2 levels so input/output are close
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# extra metal is for the gnd connection U
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self.width = self.num_top_half * self.inv.width + 2*drc["metal1_to_metal1"] + 0.5*drc["minwidth_metal1"]
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self.height = 2 * self.inv.height
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self.height = len(self.fanout_list)*self.inv.height
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self.width = (max(self.fanout_list)+1) * self.inv.width
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self.add_inv_list()
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self.add_inverters()
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def create_inv_list(self):
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"""
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Generate a list of inverters. Each inverter has a stage
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number and a flag indicating if it is a dummy load. This is
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the order that they will get placed too.
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"""
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# First stage is always 0 and is not a dummy load
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self.inv_list=[[0,False]]
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for stage_num,fanout_size in zip(range(len(self.fanout_list)),self.fanout_list):
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for i in range(fanout_size-1):
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# Add the dummy loads
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self.inv_list.append([stage_num+1, True])
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# Add the gate to drive the next stage
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self.inv_list.append([stage_num+1, False])
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def add_inv_list(self):
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def add_inverters(self):
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""" Add the inverters and connect them based on the stage list """
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dummy_load_counter = 1
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self.inv_inst_list = []
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for i in range(self.num_inverters):
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# First place the gates
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if i < self.num_top_half:
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# add top level that is upside down
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inv_offset = vector(i * self.inv.width, 2 * self.inv.height)
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inv_mirror="MX"
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self.driver_inst_list = []
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self.rightest_load_inst = {}
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self.load_inst_map = {}
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for stage_num,fanout_size in zip(range(len(self.fanout_list)),self.fanout_list):
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if stage_num % 2:
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inv_mirror = "MX"
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inv_offset = vector(0, (stage_num+1)* self.inv.height)
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else:
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# add bottom level from right to left
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inv_offset = vector((self.num_inverters - i) * self.inv.width, 0)
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inv_mirror="MY"
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cur_inv=self.add_inst(name="dinv{}".format(i),
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inv_mirror = "R0"
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inv_offset = vector(0, stage_num * self.inv.height)
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# Add the inverter
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cur_driver=self.add_inst(name="dinv{}".format(stage_num),
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mod=self.inv,
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offset=inv_offset,
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mirror=inv_mirror)
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# keep track of the inverter instances so we can use them to get the pins
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self.inv_inst_list.append(cur_inv)
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self.driver_inst_list.append(cur_driver)
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# Second connect them logically
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cur_stage = self.inv_list[i][0]
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next_stage = self.inv_list[i][0]+1
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if i == 0:
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input = "in"
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# Hook up the driver
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if stage_num+1==len(self.fanout_list):
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stageout_name = "out"
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else:
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input = "s{}".format(cur_stage)
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if i == self.num_inverters-1:
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output = "out"
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else:
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output = "s{}".format(next_stage)
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# if the gate is a dummy load don't connect the output
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# else reset the counter
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if self.inv_list[i][1]:
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output = output+"n{0}".format(dummy_load_counter)
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dummy_load_counter += 1
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stageout_name = "dout_{}".format(stage_num+1)
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if stage_num == 0:
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stagein_name = "in"
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else:
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dummy_load_counter = 1
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self.connect_inst(args=[input, output, "vdd", "gnd"])
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if i != 0:
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=cur_inv.get_pin("A").center())
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stagein_name = "dout_{}".format(stage_num)
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self.connect_inst([stagein_name, stageout_name, "vdd", "gnd"])
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# Now add the dummy loads to the right
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self.load_inst_map[cur_driver]=[]
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for i in range(fanout_size):
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inv_offset += vector(self.inv.width,0)
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cur_load=self.add_inst(name="dload_{0}_{1}".format(stage_num,i),
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mod=self.inv,
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offset=inv_offset,
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mirror=inv_mirror)
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# Fanout stage is always driven by driver and output is disconnected
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disconnect_name = "n_{0}_{1}".format(stage_num,i)
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self.connect_inst([stageout_name, disconnect_name, "vdd", "gnd"])
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# Keep track of all the loads to connect their inputs as a load
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self.load_inst_map[cur_driver].append(cur_load)
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else:
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# Keep track of the last one so we can add the the wire later
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self.rightest_load_inst[cur_driver]=cur_load
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def add_route(self, pin1, pin2):
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""" This guarantees that we route from the top to bottom row correctly. """
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pin1_pos = pin1.center()
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@@ -135,79 +122,88 @@ class delay_chain(design.design):
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# Written this way to guarantee it goes right first if we are switching rows
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self.add_path("metal2", [pin1_pos, vector(pin1_pos.x,mid_point.y), mid_point, vector(mid_point.x,pin2_pos.y), pin2_pos])
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def route_inv(self):
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def route_inverters(self):
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""" Add metal routing for each of the fanout stages """
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start_inv = end_inv = 0
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for fanout in self.fanout_list:
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# end inv number depends on the fan out number
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end_inv = start_inv + fanout
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start_inv_inst = self.inv_inst_list[start_inv]
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=start_inv_inst.get_pin("Z").center()),
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# route from output to first load
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start_inv_pin = start_inv_inst.get_pin("Z")
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load_inst = self.inv_inst_list[start_inv+1]
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load_pin = load_inst.get_pin("A")
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self.add_route(start_inv_pin, load_pin)
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next_inv = start_inv+2
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while next_inv <= end_inv:
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prev_load_inst = self.inv_inst_list[next_inv-1]
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prev_load_pin = prev_load_inst.get_pin("A")
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load_inst = self.inv_inst_list[next_inv]
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load_pin = load_inst.get_pin("A")
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self.add_route(prev_load_pin, load_pin)
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next_inv += 1
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# set the start of next one after current end
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start_inv = end_inv
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for i in range(len(self.driver_inst_list)):
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inv = self.driver_inst_list[i]
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for load in self.load_inst_map[inv]:
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# Drop a via on each A pin
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a_pin = load.get_pin("A")
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=a_pin.center(),
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rotate=90)
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self.add_via_center(layers=("metal2","via2","metal3"),
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offset=a_pin.center(),
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rotate=90)
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# Route an M3 horizontal wire to the furthest
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z_pin = inv.get_pin("Z")
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a_pin = inv.get_pin("A")
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a_max = self.rightest_load_inst[inv].get_pin("A")
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=a_pin.center(),
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rotate=90)
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=z_pin.center(),
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rotate=90)
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self.add_via_center(layers=("metal2","via2","metal3"),
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offset=z_pin.center(),
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rotate=90)
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self.add_path("metal3",[z_pin.center(), a_max.center()])
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# Route Z to the A of the next stage
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if i+1 < len(self.driver_inst_list):
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z_pin = inv.get_pin("Z")
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next_inv = self.driver_inst_list[i+1]
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next_a_pin = next_inv.get_pin("A")
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y_mid = (z_pin.cy() + next_a_pin.cy())/2
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mid1_point = vector(z_pin.cx(), y_mid)
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mid2_point = vector(next_a_pin.cx(), y_mid)
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self.add_path("metal2",[z_pin.center(), mid1_point, mid2_point, next_a_pin.center()])
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def add_layout_pins(self):
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""" Add vdd and gnd rails and the input/output. Connect the gnd rails internally on
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the top end with no input/output to obstruct. """
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vdd_pin = self.inv.get_pin("vdd")
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gnd_pin = self.inv.get_pin("gnd")
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for i in range(3):
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(offset,y_dir)=self.get_gate_offset(0, self.inv.height, i)
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rail_width = self.num_top_half * self.inv.width
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if i % 2:
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=offset + vdd_pin.ll().scale(1,y_dir),
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width=rail_width,
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height=drc["minwidth_metal1"])
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else:
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self.add_layout_pin(text="gnd",
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layer="metal1",
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offset=offset + gnd_pin.ll().scale(1,y_dir),
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width=rail_width,
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height=drc["minwidth_metal1"])
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# Use the right most parts of the gnd rails and add a U connector
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# We still have the two gnd pins, but it is an either-or connect
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gnd_pins = self.get_pins("gnd")
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gnd_start = gnd_pins[0].rc()
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gnd_mid1 = gnd_start + vector(2*drc["metal1_to_metal1"],0)
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gnd_end = gnd_pins[1].rc()
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gnd_mid2 = gnd_end + vector(2*drc["metal1_to_metal1"],0)
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#self.add_wire(("metal1","via1","metal2"), [gnd_start, gnd_mid1, gnd_mid2, gnd_end])
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self.add_path("metal1", [gnd_start, gnd_mid1, gnd_mid2, gnd_end])
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for driver in self.driver_inst_list:
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vdd_pin = driver.get_pin("vdd")
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=vdd_pin.ll(),
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width=self.width,
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height=vdd_pin.height())
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gnd_pin = driver.get_pin("gnd")
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self.add_layout_pin(text="gnd",
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layer="metal1",
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offset=gnd_pin.ll(),
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width=self.width,
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height=gnd_pin.height())
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# input is A pin of first inverter
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a_pin = self.inv_inst_list[0].get_pin("A")
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a_pin = self.driver_inst_list[0].get_pin("A")
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=a_pin.center(),
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rotate=90)
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self.add_layout_pin(text="in",
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layer="metal1",
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offset=a_pin.ll(),
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layer="metal2",
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offset=a_pin.ll().scale(1,0),
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width=a_pin.width(),
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height=a_pin.height())
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height=a_pin.cy())
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# output is Z pin of last inverter
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z_pin = self.inv_inst_list[-1].get_pin("Z")
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# output is A pin of last load inverter
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last_driver_inst = self.driver_inst_list[-1]
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a_pin = self.rightest_load_inst[last_driver_inst].get_pin("A")
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=a_pin.center(),
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rotate=90)
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mid_point = vector(a_pin.cx()+3*self.m2_width,a_pin.cy())
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self.add_path("metal2",[a_pin.center(), mid_point, mid_point.scale(1,0)])
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self.add_layout_pin(text="out",
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layer="metal1",
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offset=z_pin.ll().scale(0,1),
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width=z_pin.lx())
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layer="metal2",
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offset=mid_point.scale(1,0))
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