Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array.

2026-08-30 01:48:33 +02:00 · 2018-03-23 08:12:47 -07:00
parent c020d74f26
commit ed8eaed54f
16 changed files with 1184 additions and 777 deletions
@@ -33,6 +33,9 @@ class bitcell_array(design.design):
        self.add_pins()
        self.create_layout()
        self.add_layout_pins()
+        
+        self.offset_all_coordinates()
+        
        self.DRC_LVS()

    def add_pins(self):