luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

write_driver/sense_amp/precharge arrays: Allow y axis mirroring 

since the bitlines alternate in the bitcell array we also need to mirror
the port_data elements.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2020-01-27 17:20:48 +01:00
parent dd1afe0313
commit ed66fca031
3 changed files with 39 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
compiler/modules/precharge_array.py
View File

@ -107,9 +107,19 @@ class precharge_array(design.design):
def place_insts(self): def place_insts(self):
""" Places precharge array by horizontally tiling the precharge cell""" """ Places precharge array by horizontally tiling the precharge cell"""
from tech import cell_properties
xoffset = 0
for i in range(self.columns): for i in range(self.columns):
offset = vector(self.pc_cell.width * i, 0) tempx = xoffset
self.local_insts[i].place(offset) if cell_properties.bitcell.mirror.y and (i + 1) % 2:
mirror = "MY"
tempx = tempx + self.pc_cell.width
else:
mirror = ""
offset = vector(tempx, 0)
self.local_insts[i].place(offset=offset, mirror=mirror)
xoffset = xoffset + self.pc_cell.width
def get_en_cin(self): def get_en_cin(self):
"""Get the relative capacitance of all the clk connections in the precharge array""" """Get the relative capacitance of all the clk connections in the precharge array"""

19
compiler/modules/sense_amp_array.py
View File

@ -84,14 +84,27 @@ class sense_amp_array(design.design):
"en", "vdd", "gnd"]) "en", "vdd", "gnd"])
def place_sense_amp_array(self): def place_sense_amp_array(self):
from tech import cell_properties
if self.bitcell.width > self.amp.width: if self.bitcell.width > self.amp.width:
amp_spacing = self.bitcell.width * self.words_per_row amp_spacing = self.bitcell.width * self.words_per_row
else: else:
amp_spacing = self.amp.width * self.words_per_row amp_spacing = self.amp.width * self.words_per_row
for i in range(0,self.word_size): for i in range(0,self.word_size):
amp_position = vector(amp_spacing * i, 0) xoffset = amp_spacing * i
self.local_insts[i].place(amp_position)
# align the xoffset to the grid of bitcells. This way we
# know when to do the mirroring.
grid_x = int(xoffset / self.amp.width)
if cell_properties.bitcell.mirror.y and grid_x % 2:
mirror = "MY"
xoffset = xoffset + self.amp.width
else:
mirror = ""
amp_position = vector(xoffset, 0)
self.local_insts[i].place(offset=amp_position,mirror=mirror)
def add_layout_pins(self): def add_layout_pins(self):

13
compiler/modules/write_driver_array.py
View File

@ -106,14 +106,23 @@ class write_driver_array(design.design):
def place_write_array(self): def place_write_array(self):
from tech import cell_properties
if self.bitcell.width > self.driver.width: if self.bitcell.width > self.driver.width:
self.driver_spacing = self.bitcell.width self.driver_spacing = self.bitcell.width
else: else:
self.driver_spacing = self.driver.width self.driver_spacing = self.driver.width
for i in range(0,self.columns,self.words_per_row): for i in range(0,self.columns,self.words_per_row):
index = int(i/self.words_per_row) index = int(i/self.words_per_row)
base = vector(i * self.driver_spacing, 0) xoffset = i * self.driver_spacing
self.driver_insts[index].place(base)
if cell_properties.bitcell.mirror.y and i % 2:
mirror = "MY"
xoffset = xoffset + self.driver.width
else:
mirror = ""
base = vector(xoffset, 0)
self.driver_insts[index].place(offset=base, mirror=mirror)
def add_layout_pins(self): def add_layout_pins(self):