mirror of https://github.com/VLSIDA/OpenRAM.git
Only add drc errors from compiler
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@ -802,7 +802,8 @@ class lib:
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# information of checks
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# information of checks
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# run it only the first time
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# run it only the first time
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datasheet.write("{0},{1},".format(self.sram.drc_errors, self.sram.lvs_errors))
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if OPTS.top_process != "memchar":
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datasheet.write("{0},{1},".format(self.sram.drc_errors, self.sram.lvs_errors))
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# write area
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# write area
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datasheet.write(str(self.sram.width * self.sram.height) + ',')
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datasheet.write(str(self.sram.width * self.sram.height) + ',')
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