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SRAM layout and functional tests with spare cols

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This commit is contained in:
Aditi Sinha
2020-06-03 12:31:30 +00:00
parent c7d86b21ae
commit eb0c595dbe
12 changed files with 373 additions and 77 deletions
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compiler/modules/bank.py
+5 -5
View File
@@ -105,7 +105,7 @@ class bank(design.design):
for bit in range(self.num_wmasks):
self.add_pin("bank_wmask{0}_{1}".format(port, bit), "INPUT")
for bit in range(self.num_spare_cols):
self.add_pin("spare_wen{0}_{1}".format(port, bit), "INPUT")
self.add_pin("bank_spare_wen{0}_{1}".format(port, bit), "INPUT")
for port in self.all_ports:
self.add_pin("wl_en{0}".format(port), "INPUT")
self.add_pin("vdd", "POWER")
@@ -442,7 +442,7 @@ class bank(design.design):
for bit in range(self.num_wmasks):
temp.append("bank_wmask{0}_{1}".format(port, bit))
for bit in range(self.num_spare_cols):
temp.append("spare_wen{0}_{1}".format(port, bit))
temp.append("bank_spare_wen{0}_{1}".format(port, bit))
temp.extend(["vdd", "gnd"])
self.connect_inst(temp)
@@ -725,15 +725,15 @@ class bank(design.design):
din_name = "din{0}_{1}".format(port, row)
self.copy_layout_pin(self.port_data_inst[port], data_name, din_name)
if self.word_size:
if self.write_size:
for row in range(self.num_wmasks):
wmask_name = "bank_wmask_{}".format(row)
bank_wmask_name = "bank_wmask{0}_{1}".format(port, row)
self.copy_layout_pin(self.port_data_inst[port], wmask_name, bank_wmask_name)
for col in range(self.num_spare_cols):
sparecol_name = "spare_wen{}".format(col)
bank_sparecol_name = "spare_wen{0}_{1}".format(port, col)
sparecol_name = "bank_spare_wen{}".format(col)
bank_sparecol_name = "bank_spare_wen{0}_{1}".format(port, col)
self.copy_layout_pin(self.port_data_inst[port], sparecol_name, bank_sparecol_name)
def channel_route_bitlines(self, inst1, inst2, num_bits,
compiler/modules/control_logic.py
+2 -2
View File
@@ -107,7 +107,7 @@ class control_logic(design.design):
# clk_buf drives a flop for every address
addr_flops = math.log(self.num_words, 2) + math.log(self.words_per_row, 2)
# plus data flops and control flops
num_flops = addr_flops + self.word_size + self.num_control_signals
num_flops = addr_flops + self.word_size + self.num_spare_cols + self.num_control_signals
# each flop internally has a FO 5 approximately
# plus about 5 fanouts for the control logic
clock_fanout = 5 * num_flops + 5
@@ -135,7 +135,7 @@ class control_logic(design.design):
# s_en drives every sense amp
self.sen_and3 = factory.create(module_type="pand3",
size=self.word_size,
size=self.word_size + self.num_spare_cols,
height=dff_height)
self.add_mod(self.sen_and3)
compiler/modules/port_data.py
+7 -7
View File
@@ -138,7 +138,7 @@ class port_data(design.design):
for bit in range(self.num_wmasks):
self.add_pin("bank_wmask_{}".format(bit), "INPUT")
for bit in range(self.num_spare_cols):
self.add_pin("spare_wen{}".format(bit), "INPUT")
self.add_pin("bank_spare_wen{}".format(bit), "INPUT")
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
@@ -387,12 +387,12 @@ class port_data(design.design):
for i in range(self.num_wmasks):
temp.append("wdriver_sel_{}".format(i))
for i in range(self.num_spare_cols):
temp.append("spare_wen{}".format(i))
temp.append("bank_spare_wen{}".format(i))
elif self.num_spare_cols and not self.write_size:
temp.append("w_en")
for i in range(self.num_spare_cols):
temp.append("spare_wen{}".format(i))
temp.append("bank_spare_wen{}".format(i))
else:
temp.append("w_en")
temp.extend(["vdd", "gnd"])
@@ -627,9 +627,9 @@ class port_data(design.design):
start_bit=0
if self.port==0:
off=1
off = 1
else:
off=0
off = 0
if self.num_spare_cols != 0 and self.col_addr_size>0:
@@ -722,11 +722,11 @@ class port_data(design.design):
self.copy_layout_pin(self.write_driver_array_inst, "en_{}".format(bit), "wdriver_sel_{}".format(bit))
for bit in range(self.num_spare_cols):
# Add spare columns' en_{} pins
self.copy_layout_pin(self.write_driver_array_inst, "en_{}".format(bit + self.num_wmasks), "spare_wen{}".format(bit))
self.copy_layout_pin(self.write_driver_array_inst, "en_{}".format(bit + self.num_wmasks), "bank_spare_wen{}".format(bit))
elif self.num_spare_cols and not self.write_mask_and_array_inst:
self.copy_layout_pin(self.write_driver_array_inst, "en_0", "w_en")
for bit in range(self.num_spare_cols):
self.copy_layout_pin(self.write_driver_array_inst, "en_{}".format(bit + 1), "spare_wen{}".format(bit))
self.copy_layout_pin(self.write_driver_array_inst, "en_{}".format(bit + 1), "bank_spare_wen{}".format(bit))
else:
self.copy_layout_pin(self.write_driver_array_inst, "en", "w_en")
if self.write_mask_and_array_inst:
compiler/modules/write_driver_array.py
+10 -7
View File
@@ -142,7 +142,7 @@ class write_driver_array(design.design):
offset = self.num_wmasks
else:
offset = 1
name = "write_driver{}".format(index)
name = "write_driver{}".format(self.columns + i)
self.driver_insts[index]=self.add_inst(name=name,
mod=self.driver)
@@ -234,27 +234,30 @@ class write_driver_array(design.design):
for i in range(self.num_spare_cols):
inst = self.driver_insts[self.word_size + i]
en_pin = inst.get_pin(inst.mod.en_name)
self.add_layout_pin(text=self.en_name + "_{0}".format(i + self.num_wmasks),
layer="m1",
offset=inst.get_pin(inst.mod.en_name).ll(),
width=self.single_col_width - inst.get_pin(inst.mod.en_name).width())
offset=en_pin.ll(),
width=self.driver.width - en_pin.width())
elif self.num_spare_cols and not self.write_size:
# shorten enable rail to accomodate those for spare write drivers
inst = self.driver_insts[0]
en_pin = inst.get_pin(inst.mod.en_name)
self.add_layout_pin(text=self.en_name + "_{0}".format(0),
layer="m1",
offset=inst.get_pin(inst.mod.en_name).ll(),
width=self.width_regular_cols - (self.words_per_row * inst.get_pin(inst.mod.en_name).width()))
offset=en_pin.ll(),
width=self.width_regular_cols - self.words_per_row * en_pin.width())
# individual enables for every spare write driver
for i in range(self.num_spare_cols):
inst = self.driver_insts[self.word_size + i]
en_pin = inst.get_pin(inst.mod.en_name)
self.add_layout_pin(text=self.en_name + "_{0}".format(i + 1),
layer="m1",
offset=inst.get_pin(inst.mod.en_name).ll(),
width=self.single_col_width - inst.get_pin(inst.mod.en_name).width())
offset=en_pin.ll(),
width=self.driver.width - en_pin.width())
else:
inst = self.driver_insts[0]