luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix Verilog module typo. Adjust RBL route.

This commit is contained in:
mrg 2021-05-06 14:32:47 -07:00
parent c057490923
commit e995e61ea4
2 changed files with 8 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
compiler/base/verilog.py
View File

@ -70,7 +70,6 @@ class verilog:
self.vf.write(" parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary\n") self.vf.write(" parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary\n")
self.vf.write("\n") self.vf.write("\n")
self.vf.write("module {0}(\n".format(self.name))
self.vf.write("`ifdef USE_POWER_PINS\n") self.vf.write("`ifdef USE_POWER_PINS\n")
self.vf.write(" inout vdd;\n") self.vf.write(" inout vdd;\n")
self.vf.write(" inout gnd;\n") self.vf.write(" inout gnd;\n")

9
compiler/modules/delay_chain.py
View File

@ -191,13 +191,18 @@ class delay_chain(design.design):
def add_layout_pins(self): def add_layout_pins(self):
# input is A pin of first inverter # input is A pin of first inverter
# It gets routed to the left a bit to prevent pin access errors
# due to the output pin when going up to M3
a_pin = self.driver_inst_list[0].get_pin("A") a_pin = self.driver_inst_list[0].get_pin("A")
mid_loc = vector(a_pin.cx() - self.m3_pitch, a_pin.cy())
self.add_via_stack_center(from_layer=a_pin.layer, self.add_via_stack_center(from_layer=a_pin.layer,
to_layer="m2", to_layer="m2",
offset=a_pin.center()) offset=mid_loc)
self.add_path(a_pin.layer, [a_pin.center(), mid_loc])
self.add_layout_pin_rect_center(text="in", self.add_layout_pin_rect_center(text="in",
layer="m2", layer="m2",
offset=a_pin.center()) offset=mid_loc)
# output is A pin of last load/fanout inverter # output is A pin of last load/fanout inverter
last_driver_inst = self.driver_inst_list[-1] last_driver_inst = self.driver_inst_list[-1]